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MC14066B
Quad Analog Switch/Quad Multiplexer
The MC14066B consists of four independent switches capable of controlling either digital or analog signals. This quad bilateral switch is useful in signal gating, chopper, modulator, demodulator and CMOS logic implementation. The MC14066B is designed to be pin-for-pin compatible with the MC14016B, but has much lower ON resistance. Input voltage swings as large as the full supply voltage can be controlled via each independent control input.
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14 PDIP-14 P SUFFIX CASE 646 1 14 SOIC-14 D SUFFIX CASE 751A 1 14 14066B AWLYWW MC14066BCP AWLYYWW
* * * * * *
Triple Diode Protection on All Control Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Linearized Transfer Characteristics Low Noise -- 12 nV/Cycle, f 1.0 kHz typical Pin-for-Pin Replacement for CD4016, CD4016, MC14016B For Lower RON, Use The HC4066 High-Speed CMOS Device
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol VDD Vin, Vout Iin ISW PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input Current (DC or Transient) per Control Pin Switch Through Current Power Dissipation, per Package (Note 3.) Ambient Temperature Range Storage Temperature Range Lead Temperature (8-Second Soldering) Value - 0.5 to +18.0 - 0.5 to VDD + 0.5 10 25 500 - 55 to +125 - 65 to +150 260 Unit V V mA mA mW C C C
TSSOP-14 DT SUFFIX CASE 948G 1 14 SOEIAJ-14 F SUFFIX CASE 965 1 A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week
14 066B ALYW
MC14066B AWLYWW
ORDERING INFORMATION
Device MC14066BCP MC14066BD MC14066BDR2 MC14066BDT MC14066BDTEL MC14066BDTR2 MC14066BF MC14066BFEL Package PDIP-14 SOIC-14 SOIC-14 TSSOP-14 Shipping 2000/Box 55/Rail 2500/Tape & Reel 96/Rail
2. Maximum Ratings are those values beyond which damage to the device may occur. 3. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
v
v
TSSOP-14 2000/Tape & Reel TSSOP-14 2500/Tape & Reel SOEIAJ-14 SOEIAJ-14 See Note 1. See Note 1.
1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.
(c) Semiconductor Components Industries, LLC, 2000
1
March, 2000 - Rev. 3
Publication Order Number: MC14066B/D
MC14066B
PIN ASSIGNMENT
IN 1 OUT 1 OUT 2 IN 2 CONTROL 2 CONTROL 3 VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD CONTROL 1 CONTROL 4 IN 4 OUT 4 OUT 3 IN 3
BLOCK DIAGRAM
CONTROL 1 IN 1 5 CONTROL 2 IN 2 CONTROL 3 IN 3 CONTROL 4 IN 4 4 6 9 8 12 10 11 OUT 4 VDD = PIN 14 VSS = PIN 7 OUT 3 3 OUT 2 13 2 1 OUT 1
LOGIC DIAGRAM AND TRUTH TABLE (1/4 OF DEVICE SHOWN)
IN/OUT CONTROL
Control 0 = VSS 1 = VDD Switch OFF ON Logic Diagram Restrictions VSS Vin VDD VSS Vout VDD
OUT/IN
CIRCUIT SCHEMATIC (1/4 OF CIRCUIT SHOWN)
VDD
VDD VDD
VSS
VDD CMOS INPUT
VDD
VDD
VDD
300 VSS VSS
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SWITCHES IN AND OUT (Voltages Referenced to VSS) CONTROL INPUTS (Voltages Referenced to VSS) SUPPLY REQUIREMENTS (Voltages Referenced to VEE)
4. Data labeled "Typ" is not to be used for design purposes, but is intended as an indication of the IC's potential performance. 5. For voltage drops across the switch (Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e. the current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. (See first page of this data sheet.)
ELECTRICAL CHARACTERISTICS
Capacitance, Feedthrough (Switch Off)
Capacitance, Switch I/O
Off-Channel Leakage Current (Figure 6)
ON Resistance Between Any Two Channels in the Same Package
ON Resistance
Output Offset Voltage
Recommended Static or Dynamic Voltage Across the Switch (5.) (Figure 1)
Recommended Peak-to- Peak Voltage Into or Out of the Switch
Input Capacitance
Input Leakage Current
High-Level Input Voltage
Low-Level Input Voltage
Total Supply Current (Dynamic Plus Quiescent, Per Package
Quiescent Current Per Package
Power Supply Voltage Range
Characteristic
Symbol
Vswitch
ID(AV)
Ron
VOO
VDD
CI/O
CI/O
VI/O
Ron
VIH
IDD
Cin
VIL
Ioff
Iin
VDD
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
15
15
-- --
--
--
--
--
--
--
Control Inputs: Vin = VSS or VDD, VI/O Switch I/O: VSS VDD, and Vswitch 500 mV (5.)
Ron = per spec, Ioff = per spec
Ron = per spec, Ioff = per spec
Switch Off
Vin = VIL or VIH (Control) Channel to Channel or Any One Channel
Vswitch 500 mV Vin = VIL or VIH (Control), and Vin = 0 to VDD (Switch)
Vin = 0 V, No Load
Channel On
Channel On or Off
Vin = 0 or VDD
TA = 25_C only The channel component, (Vin - Vout)/Ron, is not included.)
v
Test Conditions
v
v
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MC14066B
v
(5.),
3 Min 3.5 7.0 11 3.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 - 55_C Typical 100 0.1 0.25 0.5 1.0 Max VDD 800 400 220 600 1.5 3.0 4.0 70 50 45 18 -- -- -- -- -- -- -- Min 3.5 7.0 11 3.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 (0.07 A/kHz) f + IDD (0.20 A/kHz) f + IDD (0.36 A/kHz) f + IDD 0.00001 Typ (4.) 0.05 0.005 0.010 0.015 25_C 0.47 2.75 5.50 8.25 2.25 4.50 6.75 250 120 80 5.0 10 25 10 10 10 -- -- -- 1050 500 280 100 0.1 0.25 0.5 1.0 MaxIII Min Max VDD 600 7.5 1.5 3.0 4.0 15 70 50 45 18 -- -- -- -- -- 3.5 7.0 11 3.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 125_C 1000 1200 520 300 1.0 VDD 135 95 65 300 1.5 3.0 4.0 7.5 15 30 18 -- -- -- -- -- -- -- Vp-p Unit mV V A A A nA pF pF pF V V V
II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I IIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII II I I I I I IIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII III I I I I I IIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I IIIIII IIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I IIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIIIII IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
6. The formulas given are for the typical characteristics only at 25_C. 7. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
ELECTRICAL CHARACTERISTICS (6.) (CL = 50 pF, TA = 25_C unless otherwise noted.)
Crosstalk, Control Input to Signal Output (Figure 5) VSS = - 5 Vdc (R1 = 1 k, RL = 10 k, Control tTLH = tTHL = 20 ns)
Channel Separation (Figure 4) (Vin = 5 Vp-p, RL = 1 k, fin = 8.0 MHz) (Switch A ON, Switch B OFF)
Feedthrough Attenuation (Switch OFF) VSS = - 5 Vdc (Vin = 5 Vp-p, RL = 1 k, fin = 1.0 MHz) (Figure 3)
Bandwidth (Switch ON) (Figure 3) VSS = - 5 Vdc (RL = 1 k, 20 Log (Vout/Vin) = - 3 dB, CL = 50 pF, Vin = 5 Vp-p)
Second Harmonic Distortion VSS = - 5 Vdc (Vin = 1.77 Vdc, RMS Centered @ 0.0 Vdc, RL = 10 k, f = 1.0 kHz)
Propagation Delay Times Input to Output (RL = 10 k) tPLH, tPHL = (0.17 ns/pF) CL + 15.5 ns tPLH, tPHL = (0.08 ns/pF) CL + 6.0 ns tPLH, tPHL = (0.06 ns/pF) CL + 4.0 ns
Control to Output (RL = 1 k) (Figure 2) Output "1" to High Impedance
High Impedance to Output "0"
High Impedance to Output "1"
Output "0" to High Impedance
Characteristic
VSS = - 5 Vdc
VSS = 0 Vdc
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MC14066B
tPLH, tPHL
Symbol
4 tPZH tPHZ tPZL tPLZ -- -- -- -- -- VDD Vdc 5.0 5.0 5.0 5.0 5.0 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Typ (7.) - 50 - 50 300 0.1 20 10 7.0 65 60 20 15 60 20 15 40 35 30 40 35 30 Max 120 40 30 120 40 30 80 70 60 80 70 60 40 20 15 -- -- -- -- -- mVp-p MHz Unit dB dB ns ns ns ns ns %
MC14066B
TEST CIRCUITS
Vout VC ON SWITCH CONTROL SECTION OF IC LOAD V Vout 10% 90% SOURCE Vout tPZL tPLZ 10% 20 ns VC tPZH Vin 90% 50% 10% RL Vx VDD CL
VSS tPHZ 90% Vin = VDD Vx = VSS Vin = VSS Vx = VDD
Figure 1. V Across Switch
Figure 2. Turn-On Delay Time Test Circuit and Waveforms
VC = VDD FOR BANDWIDTH TEST VC = VSS FOR FEEDTHROUGH TEST VDD - VSS 2 Vin RL VC CL Vout
VDD - VSS 2 Vin VDD RL CL
VSS VDD VSS
RL
CL
Figure 3. Bandwidth and Feedthrough Attenuation
Figure 4. Channel Separation
OFF CHANNEL UNDER TEST Vin Vout 1k RL 10 k VC = - 5.0 V TO + 5.0 V SWING CL = 50 pF CONTROL SECTION OF IC VDD A VSS
VSS VDD
Figure 5. Crosstalk, Control to Output
Figure 6. Off Channel Leakage
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MC14066B
VDD KEITHLEY 160 DIGITAL MULTIMETER 10 k VDD VSS 1 k RANGE X-Y PLOTTER
Figure 7. Channel Resistance (RON) Test Circuit
TYPICAL RESISTANCE CHARACTERISTICS
350 R ON , "ON" RESISTANCE (OHMS) R ON , "ON" RESISTANCE (OHMS) 300 250 200 150 100 50 0 - 10 - 8.0 - 6.0 - 4.0 - 2.0 0 0.2 4.0 6.0 350 300 250 200 150 100 50 0 - 10 - 8.0 - 6.0 - 4.0 - 2.0 0 0.2 4.0 6.0 8.0 10 TA = 125C 25C - 55C
TA = 125C 25C - 55C
8.0
10
Vin, INPUT VOLTAGE (VOLTS)
Vin, INPUT VOLTAGE (VOLTS)
Figure 8. VDD = 7.5 V, VSS = - 7.5 V
Figure 9. VDD = 5.0 V, VSS = - 5.0 V
700 R ON , "ON" RESISTANCE (OHMS) RON , "ON" RESISTANCE (OHMS) 600 500 400 300 TA = 125C 200 25C 100 0 - 10 - 8.0 - 6.0 - 4.0 - 2.0 0 0.2 - 55C 4.0 6.0 8.0 10
350 300 250 200 150 5.0 V 100 50 0 - 10 - 8.0 - 6.0 - 4.0 - 2.0 0 0.2 4.0 6.0 8.0 10 7.5 V TA = 25C
VDD = 2.5 V
Vin, INPUT VOLTAGE (VOLTS)
Vin, INPUT VOLTAGE (VOLTS)
Figure 10. VDD = 2.5 V, VSS = - 2.5 V
Figure 11. Comparison at 25C, VDD = - VSS
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MC14066B
APPLICATIONS INFORMATION Figure A illustrates use of the Analog Switch. The 0- to-5 volt digital control signal is used to directly control a 5 volt peak-to-peak analog signal. The digital control logic levels are determined by VDD and VSS. The VDD voltage is the logic high voltage, the VSS voltage is logic low. For the example, VDD = + 5 V = logic high at the control inputs; VSS = GND = 0 V = logic low. The maximum analog signal level is determined by VDD and VSS. The analog voltage must not swing higher than VDD or lower than VSS. The example shows a 5 volt peak-to-peak signal which allows no margin at either peak. If voltage transients above VDD and/or below VSS are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure B. These diodes should be small signal types able to absorb the maximum anticipated current surges during clipping. The absolute maximum potential difference between VDD and VSS is 18.0 volts. Most parameters are specified up to 15 volts which is the recommended maximum difference between VDD and V SS.
+5 V VDD VSS + 5.0 V 5 Vp-p ANALOG SIGNAL +5 V SWITCH IN
SWITCH OUT
5 Vp-p ANALOG SIGNAL
+ 2.5 V
GND EXTERNAL CMOS DIGITAL CIRCUITRY 0-TO-5 V DIGITAL CONTROL SIGNALS MC14066B
Figure A. Application Example
VDD DX SWITCH IN DX SWITCH OUT
VDD DX
DX
VSS
VSS
Figure B. External Germanium or Schottky Clipping Diodes
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MC14066B
PACKAGE DIMENSIONS
P SUFFIX PLASTIC DIP PACKAGE CASE 646-06 ISSUE M
14 8
B
1 7
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 --- 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 18.80 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 --- 10_ 0.38 1.01
A F N -T-
SEATING PLANE
L C
K H G D 14 PL 0.13 (0.005)
M
J M
DIM A B C D F G H J K L M N
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MC14066B
PACKAGE DIMENSIONS
D SUFFIX PLASTIC SOIC PACKAGE CASE 751A-03 ISSUE F
-A-
14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
-B-
1 7
P 7 PL 0.25 (0.010)
M
B
M
G C
R X 45 _
F
-T-
SEATING PLANE
D 14 PL 0.25 (0.010)
M
K TB
S
M A
S
J
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
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MC14066B
PACKAGE DIMENSIONS
DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948G-01 ISSUE O
14X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C --- 1.20 --- 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.50 0.60 0.020 0.024 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0_ 8_ 0_ 8_
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
N
2X
L/2
14
8
0.25 (0.010) M
L
PIN 1 IDENT. 1 7
B -U-
N F DETAIL E K K1 J J1
0.15 (0.006) T U
S
A -V-
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
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CCC EE CCC EE
SECTION N-N -W-
MC14066B
PACKAGE DIMENSIONS
F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 965-01 ISSUE O
14
8
LE Q1 E HE M_ L DETAIL P
1
7
Z D e A VIEW P
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 1.42 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.056
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
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MC14066B
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com Fax Response Line: 303-675-2167 or 800-344-3810 Toll Free USA/Canada N. American Technical Support: 800-282-9855 Toll Free USA/Canada EUROPE: LDC for ON Semiconductor - European Support German Phone: (+1) 303-308-7140 (M-F 1:00pm to 5:00pm Munich Time) Email: ONlit-german@hibbertco.com French Phone: (+1) 303-308-7141 (M-F 1:00pm to 5:00pm Toulouse Time) Email: ONlit-french@hibbertco.com English Phone: (+1) 303-308-7142 (M-F 12:00pm to 5:00pm UK Time) Email: ONlit@hibbertco.com EUROPEAN TOLL-FREE ACCESS*: 00-800-4422-3781 *Available from Germany, France, Italy, England, Ireland CENTRAL/SOUTH AMERICA: Spanish Phone: 303-308-7143 (Mon-Fri 8:00am to 5:00pm MST) Email: ONlit-spanish@hibbertco.com ASIA/PACIFIC: LDC for ON Semiconductor - Asia Support Phone: 303-675-2121 (Tue-Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong & Singapore: 001-800-4422-3781 Email: ONlit-asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-8549 Phone: 81-3-5740-2745 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local Sales Representative.
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MC14066B/D

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