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ispLSI 2064VE
3.3V In-System Programmable High Density SuperFASTTM PLD Features
* SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC -- 2000 PLD Gates -- 64 and 32 I/O Pin Versions, Four Dedicated Inputs -- 64 Registers -- High Speed Global Interconnect -- Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. -- Small Logic Block Size for Random Logic -- 100% Functional, JEDEC and Pinout Compatible with ispLSI 2064V Devices * 3.3V LOW VOLTAGE 2064 ARCHITECTURE -- Interfaces with Standard 5V TTL Devices * HIGH-PERFORMANCE E2CMOS(R) TECHNOLOGY -- fmax = 280MHz* Maximum Operating Frequency -- tpd = 3.5ns* Propagation Delay -- Electrically Erasable and Reprogrammable -- Non-Volatile -- 100% Tested at Time of Manufacture -- Unused Product Term Shutdown Saves Power * IN-SYSTEM PROGRAMMABLE -- 3.3V In-System Programmability (ISPTM) Using Boundary Scan Test Access Port (TAP) -- Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired-OR or Bus Arbitration Logic -- Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality -- Reprogram Soldered Devices for Faster Prototyping * 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE * THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs -- Enhanced Pin Locking Capability -- Three Dedicated Clock Input Pins -- Synchronous and Asynchronous Clocks -- Programmable Output Slew Rate Control -- Flexible Pin Placement -- Optimized Global Routing Pool Provides Global Interconnectivity * ispDesignEXPERTTM - LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING -- Superior Quality of Results -- Tightly Integrated with Leading CAE Vendor Tools -- Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZERTM -- PC and UNIX Platforms
*Advanced Information
Copyright (c) 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
(R)
Functional Block Diagram
Input Bus
Output Routing Pool (ORP) B7 B6 B5 B4
A0
Output Routing Pool (ORP)
Input Bus
A2
GLB
Logic Array
DQ
DQ
B1
DQ
A3 A4 A5 A6 A7
B0
Output Routing Pool (ORP)
Input Bus
0139A/2064V
Description
The ispLSI 2064VE is a High Density Programmable Logic Device available in 64 and 32 I/O-pin versions. The device contains 64 Registers, four Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2064VE features in-system programmability through the Boundary Scan Test Access Port (TAP) and is 100% IEEE 1149.1 Boundary Scan Testable. The ispLSI 2064VE offers non-volatile reprogrammability of the logic, as well as the interconnect, to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 2064VE device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1...B7 (see Figure 1). There are a total of 16 GLBs in the ispLSI 2064VE device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
September 2000
2064ve_06
1
Input Bus
A1
DQ
B2
Output Routing Pool (ORP)
Global Routing Pool (GRP)
B3
Specifications ispLSI 2064VE
Functional Block Diagram
Figure 1. ispLSI 2064VE Functional Block Diagram (64-I/O and 32-I/O Versions)
GOE 0
GOE 1
I/O 63 I/O 62 I/O 61 I/O 60
I/O 59
I/O 58 I/O 57
I/O 56
I/O 55 I/O 54 I/O 53 I/O 52
I/O 51 I/O 50 I/O 49 I/O 48
I/O 31 I/O 30 I/O 29 I/O 28
Input Bus
Generic Logic Blocks (GLBs)
I/O 27 I/O 26 I/O 25 I/O 24
Input Bus
Generic Logic Blocks (GLBs)
Megablock
B7
Output Routing Pool (ORP)
B6 B5 B4
Megablock
B7
Output Routing Pool (ORP)
B6 B5 B4
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Input Bus
Input Bus
I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 TDI/IN 0 TMS/IN 1
A2
B1
I/O 39 I/O 38 I/O 37 I/O 36 I/O 35 I/O 34 I/O 33 I/O 32 TCK/IN 3 TDO/IN 2
Input Bus
A2
B1
A3
B0
I/O 4 I/O 5 I/O 6 I/O 7 TDI/IN 0 TDO/IN 1
Input Bus
I/O 4 I/O 5 I/O 6 I/O 7
A1
Global Routing Pool (GRP)
B2
I/O 43 I/O 42 I/O 41 I/O 40
A1
Global Routing Pool (GRP)
B2
Output Routing Pool (ORP)
I/O 0 I/O 1 I/O 2 I/O 3
I/O 47
A0
B3
I/O 46 I/O 45 I/O 44
I/O 0 I/O 1 I/O 2 I/O 3
I/O 23
A0
B3
I/O 22 I/O 21 I/O 20
A3
B0
I/O 19 I/O 18 I/O 17 I/O 16 GOE0/IN 3
A4
A5
A6
A7
A4
A5
A6
A7
TMS/IN 2
CLK 0 CLK 1 CLK 2
BSCAN
Input Bus
BSCAN
Input Bus
I/O 16 I/O 17
I/O 18 I/O 19
I/O 20 I/O 21 I/O 22 I/O 23
I/O 24 I/O 25 I/O 26 I/O 27
I/O 28 I/O 29 I/O 30 I/O 31
Y0 Y1 Y2
I/O 8
I/O 9 I/O 10 I/O 11
I/O 12 I/O 13 I/O 14 I/O 15
The 64-I/O 2064VE contains 64 I/O cells, while the 32I/O version contains 32 I/O cells. Each I/O cell is directly connected to an I/O pin and can be individually programmed to be a combinatorial input, output or bi-directional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. Device pins can be safely driven to 5-Volt signal levels to support mixed-voltage systems. Eight GLBs, 32 or 16 I/O cells, two dedicated inputs and two or one ORPs are connected together to make a Megablock (see Figure 1). The outputs of the eight GLBs are connected to a set of 32 or 16 universal I/O cells by two or one ORPs. Each ispLSI 2064VE device contains two Megablocks. The GRP has as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 2064VE device are selected using the dedicated clock pins. Three dedicated clock pins (Y0,
Y1, Y2) or an asynchronous clock can be selected on a GLB basis. The asynchronous or Product Term clock can be generated in any GLB for its own clock.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the outputs of the ispLSI 2064VE are individually programmable, either as a standard totem-pole output or an open-drain output. The totem-pole output drives the specified Voh and Vol levels, whereas the open-drain output drives only the specified Vol. The Voh level on the open-drain output depends on the external loading and pull-up. This output configuration is controlled by a programmable fuse. The default configuration when the device is in bulk erased state is totem-pole configuration. The open-drain/totem-pole option is selectable through the ispDesignEXPERT software tools.
2
GOE1/Y0 RESET/Y1 TCK/Y2
0139B/2064VE
CLK 0 CLK 1 CLK 2
0139B/2064VE.32IO
RESET
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Specifications ispLSI 2064VE
Absolute Maximum Ratings 1
Supply Voltage Vcc ................................................... -0.5 to +5.4V Input Voltage Applied ..................................... -0.5 to +5.6V Off-State Output Voltage Applied .................. -0.5 to +5.6V Storage Temperature ..................................... -65 to 150C Case Temp. with Power Applied .................... -55 to 125C Max. Junction Temp. (TJ) with Power Applied ............ 150C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
SYMBOL PARAMETER Supply Voltage Input Low Voltage Input High Voltage Commercial Industrial TA = 0C to + 70C TA = -40C to + 85C MIN. 3.0 3.0 VSS - 0.5 2.0 MAX. 3.6 3.6 0.8 5.25 UNITS V V V V
Table 2-0005/2064V
VCC VIL VIH
Capacitance (TA=25C, f=1.0 MHz)
SYMBOL PARAMETER Dedicated Input Capacitance I/O Capacitance Clock and Global Output Enable Capacitance TYPICAL 8 6 10 UNITS pf pf pf TEST CONDITIONS VCC = 3.3V, VIN = 0.0V VCC = 3.3V, VI/O = 0.0V VCC = 3.3V, VY = 0.0V
Table 2-0006/2064VE
C1 C2 C3
Erase Reprogram Specifications
PARAMETER Erase/Reprogram Cycles MINIMUM 10000 MAXIMUM - UNITS Cycles
Table 2-0008/2064VE
3
Specifications ispLSI 2064VE
Switching Test Conditions
Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. GND to 3.0V 1.5 ns 10% to 90% 1.5V 1.5V See Figure 2
Table 2-0003/2064VE
Figure 2. Test Load
+ 3.3V R1 Device Output R2 C L* Test Point
Output Load Conditions (see Figure 2)
TEST CONDITION A B Active High Active Low Active High to Z at VOH -0.5V Active Low to Z at VOL +0.5V R1 316 316 316 R2 348 348 348 348 348 CL 35pF 35pF 35pF 5pF 5pF
*CL includes Test Fixture and Probe Capacitance.
0213A/2064V
C
Table 2-0004/2064V
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL PARAMETER Output Low Voltage Output High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current BSCAN Input Low Leakage Current I/O Active Pull-Up Current Output Short Circuit Current Operating Power Supply Current IOL= 8 mA IOH = -4 mA 0V VIN VIL (Max.) (VCC - 0.2)V VIN VCC V VIN 5.25V CC 0V VIN VIL 0V VIN VIL VCC = 3.3V, VOUT = 0.5V VIL = 0.0V, VIH = 3.0V fCLOCK = 1 MHz CONDITION MIN. - 2.4 - - - - - - - TYP. - - - - - - - - 90
3
MAX. UNITS 0.4 - -10 10 10 -150 -150 -100 - V V A A A A A mA mA
VOL VOH IIL IIH IIL-isp IIL-PU IOS1 ICC2, 4
Table 2-0007/2064VE 1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Measured using four 16-bit counters. 3. Typical values are at VCC = 3.3V and TA= 25C. 4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum ICC .
4
Specifications ispLSI 2064VE
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TEST COND. A A A -- -- -- A -- -- A -- A -- B C B C -- --
3
# 1 2 3 4 5 6 7 8 9
DESCRIPTION
1
-280 -- -- 280
1
-200 -- -- 200 133 200 3.0 -- 0.0 4.0 -- 0.0 -- 4.0 -- -- -- -- 2.5 2.5 4.5 7.0 -- -- -- -- 3.5 -- -- 4.5 -- 6.0 -- 8.0 8.0 5.0 5.0 -- --
MIN. MAX. MIN. MAX. 3.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
UNITS ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl
Data Propagation Delay, 4PT Bypass, ORP Bypass Data Propagation Delay Clock Frequency with Internal Feedback Clock Frequency, Max. Toggle GLB Reg. Setup Time before Clock, 4 PT Bypass GLB Reg. Clock to Output Delay, ORP Bypass GLB Reg. Hold Time after Clock, 4 PT Bypass GLB Reg. Setup Time before Clock
2
Clock Frequency with External Feedback ( tsu2 + tco1)
-- -- --
-- -- -- -- -- -- -- -- -- -- -- -- --
10 GLB Reg. Clock to Output Delay 11 GLB Reg. Hold Time after Clock 12 Ext. Reset Pin to Output Delay 13 Ext. Reset Pulse Duration 14 Input to Output Enable 15 Input to Output Disable 16 Global OE Output Enable 17 Global OE Output Disable 18 External Synchronous Clock Pulse Duration, High 19 External Synchronous Clock Pulse Duration, Low
ADVANCED INF ORMATION
1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock. 2. Standard 16-bit counter using GRP feedback. 3. Reference Switching Test Conditions section.
Table 2-0030A/2064VE
5
Specifications ispLSI 2064VE
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TEST COND. A A A -- -- -- A -- -- A -- A -- B C B C -- --
3
# 1 2 3 4 5 6 7 8 9
DESCRIPTION
1
-135 -- --
2 1
-100 -- -- 100 77 100 6.5 -- 0.0 8.0 -- 0.0 -- 6.5 -- -- -- -- 5.0 5.0 10.0 13.0 -- -- -- -- 5.0 -- -- 6.0 -- 13.5 -- 15.0 15.0 9.0 9.0 -- --
MIN. MAX. MIN. MAX. 7.5 10.0 -- -- -- -- 4.0 -- -- 5.0 -- 10.0 -- 12.0 12.0 7.0 7.0 -- --
UNITS ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl
Data Propagation Delay, 4PT Bypass, ORP Bypass Data Propagation Delay Clock Frequency with Internal Feedback Clock Frequency, Max. Toggle GLB Reg. Setup Time before Clock, 4 PT Bypass GLB Reg. Clock to Output Delay, ORP Bypass GLB Reg. Hold Time after Clock, 4 PT Bypass GLB Reg. Setup Time before Clock Clock Frequency with External Feedback ( tsu2 + tco1)
135 100 143 5.0 -- 0.0 6.0 -- 0.0 -- 5.0 -- -- -- -- 3.5 3.5
10 GLB Reg. Clock to Output Delay 11 GLB Reg. Hold Time after Clock 12 Ext. Reset Pin to Output Delay 13 Ext. Reset Pulse Duration 14 Input to Output Enable 15 Input to Output Disable 16 Global OE Output Enable 17 Global OE Output Disable 18 External Synchronous Clock Pulse Duration, High 19 External Synchronous Clock Pulse Duration, Low
1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock. 2. Standard 16-bit counter using GRP feedback. 3. Reference Switching Test Conditions section.
Table 2-0030B/2064VE
6
Specifications ispLSI 2064VE
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER Inputs #
2
DESCRIPTION
-200
-135
-100
MIN. MAX. MIN. MAX. MIN. MAX. - - - - - - - - - 1.2 1.8 - - - - 1.0 - - - - - - - 1.2 1.4 - 0.5 1.1 0.6 1.4 1.9 2.9 2.9 2.9 0.0 - - 0.3 0.4 4.3 3.9 4.0 1.5 0.5 1.5 2.0 3.0 3.0 2.0 1.2 1.4 3.6 - - - - - - - - - 1.2 3.8 - - - - 1.6 - - - - - - - 1.6 1.8 - 0.5 1.7 1.2 3.7 3.7 4.7 4.7 4.7 0.5 - - 0.3 1.1 6.1 6.9 5.0 1.5 0.5 1.6 2.0 3.4 3.4 3.6 1.6 1.8 5.8 - - - - - - - - - 1.7 4.8 - - - - 2.6 - - - - - - - 2.4 2.6 - 0.7 2.5 1.8 5.2 4.7 6.2 6.2 6.2 1.0 - - 0.3 3.1 7.1 9.1 5.6 1.7 0.7 1.6 2.0 3.4 3.4 5.6 2.4 2.6 7.1
UNITS
tio tdin
GRP
20 Input Buffer Delay 21 Dedicated Input Delay 22 GRP Delay 23 4 Product Term Bypass Path Delay (Combinatorial) 24 4 Product Term Bypass Path Delay (Registered) 25 1 Product Term/XOR Path Delay 26 20 Product Term/XOR Path Delay 27 XOR Adjacent Path Delay
3
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tgrp
GLB
t4ptbpc t4ptbpr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck
ORP
28 GLB Register Bypass Delay 29 GLB Register Setup Time before Clock 30 GLB Register Hold Time after Clock 31 GLB Register Clock to Output Delay 32 GLB Register Reset to Output Delay 33 GLB Product Term Reset to Register Delay 34 GLB Product Term Output Enable to I/O Cell Delay 35 GLB Product Term Clock Delay 36 ORP Delay 37 ORP Bypass Delay 38 Output Buffer Delay 39 Output Slew Limited Delay Adder 40 I/O Cell OE to Output Enabled 41 I/O Cell OE to Output Disabled 42 Global Output Enable 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line 45 Global Reset to GLB
torp torpbp
Outputs
tob tsl toen todis tgoe
Clocks
tgy0 tgy1/2
Global Reset
tgr
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros.
Table 2-0036/2064VE
7
Specifications ispLSI 2064VE
ispLSI 2064VE Timing Model
I/O Cell GRP Feedback Ded. In Comb 4 PT Bypass #23 GRP #22 Reg 4 PT Bypass #24 20 PT XOR Delays #25, 26, 27 Reset #45 D RST #29, 30, 31, 32 GLB Reg Bypass #28 GLB Reg Delay Q ORP Bypass #37 ORP Delay #36 #38, 39 I/O Pin (Output) GLB ORP I/O Cell
#21 I/O Delay #20
I/O Pin (Input)
Control RE PTs OE #33, 34, CK 35 Y0,1,2 GOE 0,1 #43, 44 #42
#40, 41
0491/2064
Derivations of tsu, th and tco from the Product Term Clock tsu
= = = 3.1ns = = = = 2.9ns = = = = 8.4ns = Logic + Reg su - Clock (min) (tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min)) (#20 + #22 + #26) + (#29) - (#20 + #22 + #35) (0.5 + 0.6 + 2.9) + (1.2) - (0.5 + 0.6 + 1.0) Clock (max) + Reg h - Logic (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor) (#20 + #22 + #35) + (#30) - (#20 + #22 + #26) (0.5 + 0.6 + 4.0) + (1.8) - (0.5 + 0.6 + 2.9) Clock (max) + Reg co + Output (tio + tgrp + tptck(max)) + (tgco) + (torp + tob) (#20 + #22 + #35) + (#31) + (#36 + #38) (0.5 + 0.6 + 4.0) + (0.3) + (1.5 + 1.5)
th
tco
Note: Calculations are based on timing specifications for the ispLSI 2064VE-200L.
Table 2-0042/2064VE
8
Specifications ispLSI 2064VE
Power Consumption
Power consumption in the ispLSI 2064VE device depends on two primary factors: the speed at which the device is operating and the number of Product Terms Figure 3. Typical Device Power Consumption vs fmax
160 ispLSI 2064VE 140
used. Figure 3 shows the relationship between power and operating speed.
ICC (mA)
120
100 80
0
50
100
150
200
fmax (MHz)
Notes: Configuration of four 16-bit counters Typical current at 3.3V, 25 C
ICC can be estimated for the ispLSI 2064VE using the following equation: ICC(mA) = 8 + (# of PTs * 0.67) + (# of Nets * Max. Freq. * 0.0045) Where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max freq = Highest Clock Frequency to the device (in MHz) The ICC estimate is based on typical conditions (VCC = 3.3V, room temperature) and an assumption of two GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified.
0127/2064VE
9
Specifications ispLSI 2064VE
64-I/O Signal Descriptions
Signal Name RESET GOE 0, GOE1 Y0, Y1, Y2 BSCAN TDI/IN 0 Global Output Enable input pins. Dedicated Clock Input - These clock inputs are connected to one of the clock inputs of all the GLBs in the device. Input - Dedicated in-system programming Boundary Scan enable input pin. This pin is brought low to enable the programming mode. The TMS, TDI, TDO and TCK controls become active. Input - This pin performs two functions. When BSCAN is logic low, it functions as an input pin to load programming data into the device. TDI/IN0 is also used as one of the two control pins for the ISP State Machine. When BSCAN is high, it functions as a dedicated input pin. Input - This pin performs two functions. When BSCAN is logic low, it functions as a clock pin for the Boundary Scan state machine. When BSCAN is high, it functions as a dedicated input pin. Input - This pin performs two functions. When BSCAN is logic low, it functions as a mode control pin for the Boundary Scan state machine. When BSCAN is high, it functions as a dedicated input pin. Output/Input - This pin performs two functions. When BSCAN is logic low, it functions as an output pin to read serial shift register data. When BSCAN is high, it functions as a dedicated input pin. Ground (GND) Vcc No Connect Input/Output Pins - These are the general purpose I/O pins used by the logic array. Description Active Low (0) Reset pin resets all the registers in the device.
TCK/IN 3 TMS/IN 1 TDO/IN 2 GND VCC NC1 I/O
1. NC pins are not to be connected to any active signals, VCC or GND.
32-I/O Signal Descriptions
Signal Name GOE 0/IN 3 GOE 1/Y0 Description This pin performs one of two functions. It can be programmed to function as a Global Output Enable pin or a Dedicated Input pin. This pin performs one of two functions. It can be programmed to function as a GLobal Output Enable or a Dedicated Clock input. This clock input is connected to one of the clock inputs of all GLBs on the device. This pin performs two functions: (1) Dedicated clock input. This clock input is brought into the Clock Deistribution Network and can optionally be routed to any GLB and/or I/O cell on the device. (2) Active Low (0) Reset pin which resets all of the registers in the device. Input - Dedicated in-system programming Boundary Scan Enable input pin. This pin is brought low to enable the programming mode. The TMS, TDI, TDO and TCK controls become active. Input - This pin performs two functions. When BSCAN is logic low, it functions as an input pin to load programming data into the device. TDI/IN0 is also used as one of the two control pins for the ISP State Machine. When BSCAN is high, it functions as a dedicated input pin. Input - This pin performs two functions. When BSCAN is logic low, it functions as a pin to control the operation of the ISP State Machine. When BSCAN is high, it functions as a dedicated input pin. Output/Input - This pin performs two functions. When BSCAN is logic low, it functions as an output pin pin to read serial shift register data. When BSCAN is high, it functions as a dedicated input pin. Input - This pin performs two functions. When BSCAN is logic low, it functions as a clock pin for the Serial Shift Register. When BSCAN is high, it functions as a dedicated clock input. This clock input is brought into the Clock Distribution Network and can optionally be routed to any GLB and/or I/O cell on the device. Ground (GND) Vcc No Connect Input/Output pins - These are the general purpose I/O pins used by the logic array.
RESET/Y1
BSCAN TDI/IN 0
TMS/IN 2 TDO/IN 1 TCK/Y2
GND VCC NC1 I/O
1. NC pins are not to be connected to any active signals, VCC or GND.
10
Specifications ispLSI 2064VE
64-I/O Signal Locations
Signal RESET GOE 0, GOE 1 Y0, Y1, Y2 BSCAN TDI/IN 0 TCK/IN 3 TMS/IN 1 TDO/IN 2 GND 100-Ball caBGA D2 F9, E1 E3, F6, F8 E5 F2 G10 J5 B6 B7, F1, G9, K6 100-Pin TQFP 11 62, 13 10, 65, 60 15 16 59 37 87 14, 39, 61, 86
I/O Locations
100 Signal caBGA 100 TQFP 44 TQFP 44 PLCC
VCC
A5, E2, F10, J4
12, 36, 63, 89
NC1
A6, A8, C3, C4, D1, D6, D8, E7, E9, E10, F4, G3, G5, H7, H8, K3, K5
4, 9, 21, 25, 31, 38, 44, 50, 54, 64, 66, 71, 75, 81, 88, 94, 100
1. NC pins are not to be connected to any active signals, VCC or GND.
32-I/O Signal Locations
Signal GOE 0/ IN 3 GOE 1/Y0 RESET/Y1 BSCAN TDI/IN 0 TMS/IN 2 TDO/IN 1 TCK/Y2 GND VCC NC1 44-Pin TQFP 40 5 29 7 8 30 18 27 17, 39 6, 28 -- 44-Pin PLCC 2 11 35 13 14 36 24 33 1, 23 12, 34 --
1. NC pins are not to be connected to any active signals, VCC or GND.
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O 33 I/O 34 I/O 35 I/O 36 I/O 37 I/O 38 I/O 39 I/O 40 I/O 41 I/O 42 I/O 43 I/O 44 I/O 45 I/O 46 I/O 47 I/O 48 I/O 49 I/O 50 I/O 51 I/O 52 I/O 53 I/O 54 I/O 55 I/O 56 I/O 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63
G1 F3 E4 H1 G2 J1 H2 K1 J2 K2 H3 J3 G4 H4 K4 H5 F5 J6 K7 H6 K8 G6 J7 K9 J8 K10 J9 J10 H9 H10 G7 G8 D10 E8 F7 C10 D9 B10 C9 A10 B9 A9 C8 B8 D7 C7 A7 C6 E6 B5 A4 C5 A3 D5 B4 A2 B3 A1 B2 B1 C2 C1 D4 D3
17 18 19 20 22 23 24 26 27 28 29 30 32 33 34 35 40 41 42 43 45 46 47 48 49 51 52 53 55 56 57 58 67 68 69 70 72 73 74 76 77 78 79 80 82 83 84 85 90 91 92 93 95 96 97 98 99 1 2 3 5 6 7 8
9 10 11 12 13 14 15 16 19 20 21 22 23 24 25 26 31 32 33 34 35 36 37 38 41 42 43 44 1 2 3 4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
15 16 17 18 19 20 21 22 25 26 27 28 29 30 31 32 37 38 39 40 41 42 43 44 3 4 5 6 7 8 9 10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
11
Specifications ispLSI 2064VE
Signal Configuration
ispLSI 2064VE 100-Ball caBGA Signal Diagram
10
9
8
7
6
5
4
3
2
1
A B C D E F G H J K
I/O 39 I/O 37 I/O 35 I/O 32 NC1
I/O 41 I/O 40 I/O 38 I/O 36 NC1
NC1
I/O 46 GND I/O 45 I/O 44 NC1
NC1
VCC
I/O 50 I/O 54 NC1 I/O 62 I/O 2 NC1 I/O 12 I/O 13 VCC
I/O 52 I/O 56 NC1 I/O 63 Y0
I/O 55 I/O 58 I/O 60
RESET
I/O 57 I/O 59 I/O 61 NC1
A B C D E F G H J K
I/O 43 I/O 42 NC1
TDO/ IN 2 I/O 47 NC1
I/O 49 I/O 51 I/O 53
I/O 33 Y2 I/O 31 NC1 I/O 24 I/O 20
I/O 48 Y1 I/O 21 I/O 19 I/O 17 GND
BSCAN
VCC
GOE 1 GND I/O 0 I/O 3 I/O 5 I/O 7
VCC TCK/ IN 3 I/O 29 I/O 27 I/O 25
GOE 0 GND I/O 28 I/O 26 I/O 23
I/O 34 I/O 30 NC1 I/O 22 I/O 18
I/O 16 NC1 I/O 15 TMS/ IN 1 NC1
I/O 1 NC1 I/O 10 I/O 11 NC1
TDI/ IN 0 I/O 4 I/O 6 I/O 8 I/O 9
I/O 14
ispLSI 2064VE
Bottom View
10
1NCs
9
8
7
6
5
4
3
2
1
100-BGA/2064VE
are not to be connected to any active signals, VCC or GND.
Note: Ball A1 indicator dot on top side of package.
12
Specifications ispLSI 2064VE
Pin Configuration
ispLSI 2064VE 100-Pin TQFP Pinout Diagram
NC1 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 NC1 I/O 51 I/O 50 I/O 49 I/O 48 VCC NC1 TDO/IN 2 GND I/O 47 I/O 46 I/O 45 I/O 44 NC1 I/O 43 I/O 42 I/O 41 I/O 40 I/O 39 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
I/O 57 I/O 58 I/O 59 1NC I/O 60 I/O 61 I/O 62 I/O 63 1NC Y0 RESET VCC GOE 1 GND BSCAN TDI/IN 0 I/O 0 I/O 1 I/O 2 I/O 3 1NC I/O 4 I/O 5 I/O 6 1NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
ispLSI 2064VE
Top View
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
NC1 I/O 38 I/O 37 I/O 36 NC1 I/O 35 I/O 34 I/O 33 I/O 32 NC1 Y1 NC1 VCC GOE 0 GND Y2 TCK/IN 3 I/O 31 I/O 30 I/O 29 I/O 28 NC1 I/O 27 I/O 26 I/O 25
I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 1NC I/O 12 I/O 13 I/O 14 I/O 15 VCC TMS/IN 1 1NC GND I/O 16 I/O 17 I/O 18 I/O 19 1NC I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 1NC
100 TQFP/2064VE
1. NC pins are not to be connected to any active signals, VCC or GND.
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
13
Specifications ispLSI 2064VE
Pin Configuration
ispLSI 2064VE 44-Pin PLCC Pinout Diagram
GOE 0/IN 3
I/O 27
I/O 26 I/O 25
I/O 24
I/O 23
I/O 22
I/O 21
6 5 4 3 2 1 44 43 42 41 40 I/O 28 I/O 29 I/O 30 I/O 31 GOE1/Y0 VCC BSCAN TDI/IN 0 I/O 0 I/O 1 I/O 2 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 39 38 37 36 35 34 33 32 31 30 29 I/O 18 I/O 17 I/O 16 TMS/IN 2 RESET/Y1 VCC TCK/Y2 I/O 15 I/O 14 I/O 13 I/O 12
ispLSI 2064VE
Top View
GND
I/O 3
I/O 4 I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
TDO/IN 1
I/O 10 I/O 11
I/O 20 I/O 19
GND
44 PLCC/2064VE
Pin Configuration
ispLSI 2064VE 44-Pin TQFP Pinout Diagram
GOE 0/IN 3 I/O 27 I/O 26 I/O 25 I/O 24 GND I/O 23 I/O 22 I/O 21 I/O 20 I/O 19
44 43 42 41 40 39 38 37 36 35 34 I/O 28 I/O 29 I/O 30 I/O 31 GOE1/Y0 VCC BSCAN TDI/IN 0 I/O 0 I/O 1 I/O 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
GND TDO/IN 1 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11
33 32 31 30
I/O 18 I/O 17 I/O 16 TMS/IN 2 RESET/Y1 VCC TCK/Y2 I/O 15 I/O 14 I/O 13 I/O 12
ispLSI 2064VE
Top View
29 28 27 26 25 24 23
44 TQFP/2064VE
14
Specifications ispLSI 2064VE
Part Number Description
ispLSI 2064VE - XXX X XXXX X
Device Family Device Number Speed 280 = 280 MHz fmax* 200 = 200 MHz fmax 135 = 135 MHz fmax 100 = 100 MHz fmax
*Advanced Information
Grade Blank = Commercial I = Industrial Package T100 = 100-Pin TQFP B100 = 100-Ball caBGA T44 = 44-Pin TQFP J44 = 44-Pin PLCC Power L = Low
0212/2064VE
ispLSI 2064VE Ordering Information
COMMERCIAL
FAMILY fmax (MHz) 280 280 280 200 200 200 ispLSI 200 135 135 135 135 100 100 100 100 *Advanced Information tpd (ns) 3.5 3.5 3.5 4.5 4.5 4.5 4.5 7.5 7.5 7.5 7.5 10 10 10 10 I/Os 64 64 32 64 64 32 32 64 64 32 32 64 64 32 32 ORDERING NUMBER ispLSI 2064VE-280LT100* ispLSI 2064VE-280LB100* ispLSI 2064VE-280LT44* ispLSI 2064VE-200LT100 ispLSI 2064VE-200LB100 ispLSI 2064VE-200LJ44 ispLSI 2064VE-200LT44 ispLSI 2064VE-135LT100 ispLSI 2064VE-135LB100 ispLSI 2064VE-135LJ44 ispLSI 2064VE-135LT44 ispLSI 2064VE-100LT100 ispLSI 2064VE-100LB100 ispLSI 2064VE-100LJ44 ispLSI 2064VE-100LT44 PACKAGE 100-Pin TQFP 100-Ball caBGA 44-Pin TQFP 100-Pin TQFP 100-Ball caBGA 44-Pin PLCC 44-Pin TQFP 100-Pin TQFP 100-Ball caBGA 44-Pin PLCC 44-Pin TQFP 100-Pin TQFP 100-Ball caBGA 44-Pin PLCC 44-Pin TQFP
Table 2-0041A/2064VE
INDUSTRIAL
FAMILY ispLSI fmax (MHz) 135 135 tpd (ns) 7.5 7.5 I/Os 64 32 ORDERING NUMBER ispLSI 2064VE-135LT100I ispLSI 2064VE-135LT44I PACKAGE 100-Pin TQFP 44-Pin TQFP
Table 2-0041B/2064VE
15

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