View ICS9248-110_26355.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Integrated Circuit Systems, Inc.
ICS9248-110
AMD-K7TM System Clock Chip
Recommended Application: AMD-K7 based systems Output Features: * 3 differential pair open drain CPU clocks (2.7V external pull-up; up to 150MHz achieviable through I2C) * 2 - AGPCLK @ 3.3V * 8 - PCI @3.3V, including 1 free running * 1 - 48MHz @ 3.3V * 1 - 24/48MHz @ 3.3V * 2- REF @3.3V, 14.318MHz. Features: * Up to 150MHz frequency support * Support power management: CPU, PCI, stop and Power down Mode from I2C programming. * Spread spectrum for EMI control -0.5% down spread * Uses external 14.318MHz crystal * FS pins for frequency select Key Specifications: * CPU - CPU: <250ps * AGP-AGP: <250ps * PCI - PCI: <400ps * CPU - SDRAM_OUT: <400ps * CPU-AGP <250ps
Pin Configuration
**FS0/REF0 **FS1/REF1 GNDREF X1 X2 GNDPCI PCICLK_F PCICLK0 VDDPCI PCICLK1 PCICLK2 GNDPCI PCICLK3 PCICLK4 VDDPCI PCICLK5 PCICLK6 VDDAGP AGP0 AGP1 GNDAGP VDD48 48MHz SEL24_48#/24-48MHz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDREF GNDSD SDRAM_OUT VDDSD RESERVED CPUCLKC2 CPUCLKT2 GNDCPU CUCLKC1 CPUCLKT1 GND CPUCLKC0 CPUCLKT0 RESERVED VDD GND PCI_STOP# CPU_STOP PD# SPREAD# FS2* SDATA SCLK GND48
48-Pin 300mil SSOP
* Internal 120K pullup resistor on indicated inputs ** Internal 240K pullup resistor on indicated inputs
Block Diagram
X1 X2
OSC
REF (1:0)
CPU_STOP#
Functionality
FS (2:0) SPREAD#
PLL
CPU STOP
CPUCLKT (2:0) CPUCLKC (2:0) SDRAM_OUT
FS2 0 0 0 0 1 1 1 1
FS1 0 0 1 1 0 0 1 1
FS0 0 1 0 1 0 1 0 1
/2
PD#
/3
X2 PCI STOP
AGP (1:0) PCICLK (6:0)
PCI_STOP#
PCICLK_F
PLL2 /2
SEL24_48#
48MHz 24_48MHz
CPU, SDRAM 90 95 100.99 115 100.7 103 105 110
ICS9248-110
PCI 30.00 31.67 33.66 38.33 33.57 34.33 35.00 36.67
AGP 60.00 63.33 67.33 76.67 67.13 68.67 70.00 73.33
9248-110 Rev C 01/08/01 Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9248-110
Pin Descriptions
PIN NUMBER 2, 1 3 4 5 6, 12 7 17, 16, 14, 13, 11, 10, 8 9, 15 18 20, 19 21 34 33 22 23 24 25 26 27 28 29 30 31 32 46 34 35, 44 42, 39, 36 43, 40, 37 38, 41 45 47 48 PIN NAME FS (1:0) REF (1:0) GNDREF X1 X2 GNDPCI PCICLK_F PCICLK (6:0) VDDPCI VDDAGP AGP (1:0) GNDAGP VDD GND VDD48 48MHz SEL24-48# 24-48MHz GND48 SCLK SDATA FS2 SPREAD# PD# CPU_STOP# PCI_STOP# SDRAM_OUT VDD RESERVED CPUCLKT (2:0) CPUCLKC (2:0) GNDCPU VDDSD GNDSD VDDREF TYPE IN OUT PWR IN OUT PWR OUT OUT PWR PWR OUT PWR PWR PWR PWR OUT IN OUT PWR IN I/O IN IN IN IN IN OUT PWR N/C OUT OUT PWR PWR PWR PWR DESCRIPTION Frequency Select pins, has pull-up to VDD 14.318MHz clock output Ground for REF outputs XTAL_IN 14.318MHz Crystal input, has internal 33pF load cap and feed back resistor from X2 XTAL_OUT Crystal output, has internal load cap 33pF Ground for PCI outputs Free Running PCI output. Not affected by the PCI_STOP# input. PCI clock outputs. TTL compatible 3.3V Power for PCICLK outputs, nominally 3.3V Power for AGP outputs, nominally 3.3V AGP outputs defined as 2X PCI. These may not be stopped. Ground for AGP clock outputs Isolated power for core, nominally 3.3V Isolated ground for core Power for USB, FDC outputs nominally 3.3V 48MHz output Selects 24 or 48MHz output for pin 24 Low = 48MHz High = 24MHz Fixed clock out selectable through SEL24-48# Ground for 48MHz outputs Clock input for I2C Data pin for I2C circuitry 5V tolerant Frequency Select pin, has pull-up to VDD Enables Spread Spectrum feature when LOW. Down Spread 0.5% modulation frequency =50KHz Powers down chip, active low. Internal PLL & all outputs are disabled. Halts CPUCLKs. CPUCLKTs driven LOW wheras CPUCLKC is driven HIGH when this pin is asserted (Active LOW). Halts PCI Bus at logic "0" level when driven low. PCICLK_F is not affected by this pin Reference clock for SDRAM zero delay buffer Isolated power for core Furture CPU power rail "True" clocks of differential pair CPU outputs. These open drain outputs need an external 1.5V pull-up. "Complementory" clocks of differental pair CPU output. These open drain outputs need an external 1.5V pull_up. Ground for CPUCLK outputs. Power for SDRAM_OUT pin. Nominally 3.3V Ground for SDRAM_OUT pins Power for REF, X1, X2, nominally 3.3V
Third party brands and names are the property of their respective owners.
2
ICS9248-110
General Description
The ICS9248-110 is a main clock synthesizer chip for AMD-K7 based systems. This provides all clocks required for such a system when used with a Zero Delay Buffer Chip such as the ICS9179-06. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-110 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation. CPU_STOP# is synchronized by the ICS9248-110. All other clocks will continue to run while the CPUCLKs clocks are disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
INTERNAL CPUCLK PCICLK CPU_STOP# PCI_STOP# (High) PD# (High) CPUCLKT CPUCLKC
Notes: 1. All timing is referenced to the internal CPUCLK. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside the ICS9248-110. 3. All other clocks continue to run undisturbed. 4. PD# and PCI_STOP# are shown in a high (true) state.
Third party brands and names are the property of their respective owners.
3
ICS9248-110
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-110. It is used to turn off the PCICLK (0:5) clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-110 internally. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
CPUCLK (Internal)
PCICLK (Internal) PCICLK (Free-runningl) CPU_STOP#
PCI_STOP# PWR_DWN#
PCICLK (External)
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9248. 3. All other clocks continue to run undisturbed. 4. PD# and CPU_STOP# are shown in a high (true) state.
Third party brands and names are the property of their respective owners.
4
ICS9248-110
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
PD#
CPUCLKT CPUCLKC
PCICLK VCO Crystal
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-110 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
Third party brands and names are the property of their respective owners.
5
ICS9248-110
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS9248110 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad
Via to VDD 2K W
8.2K W Clock trace to load Series Term. Res.
Fig. 1
Third party brands and names are the property of their respective owners.
6
ICS9248-110
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 6 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Stop Bit ICS (Slave/Receiver)
How to Read:
* * * * * * * * Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 6 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
* * * * * * * *
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK
ACK Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Stop Bit
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
Third party brands and names are the property of their respective owners.
7
ICS9248-110
I2C Command Bitmaps
Byte 6: SDRAM Clock & Generator Mode Control Register
Bit 7 Description Spread Spectrum enable (+/- 0.25% center spread) 1=ON 0=OFF FS2 FS1 FS0 CPU, Bit 3 Bit 2 Bit 6 Bit 5 Bit 4 SDRAM PCI 0 0 0 0 0 90 30.00 0 0 0 0 1 95 31.67 0 0 0 1 0 100.99 33.66 0 0 0 1 1 115 38.33 0 0 1 0 0 100.7 33.57 0 0 1 0 1 103 34.33 0 0 1 1 0 105 35.00 0 0 1 1 1 110 36.67 0 1 0 0 0 102 34.00 0 1 0 0 1 104 34.67 0 1 0 1 0 106 35.33 0 1 0 1 1 107 35.67 0 1 1 0 0 108 36.00 0 1 1 0 1 109 36.33 0 1 1 1 0 110 36.67 0 1 1 1 1 111 37.00 1 0 0 0 0 112 37.33 1 0 0 0 1 113 37.67 1 0 0 1 0 114 38.00 1 0 0 1 1 116 38.67 1 0 1 0 0 117 39.00 1 0 1 0 1 118 39.33 1 0 1 1 0 119 39.67 1 0 1 1 1 120 30.00 1 1 0 0 0 121 30.25 1 1 0 0 1 122 30.50 1 1 0 1 0 123 30.75 1 1 0 1 1 124 31.00 1 1 1 0 0 125 31.25 1 1 1 0 1 133.33 33.33 1 1 1 1 0 140 35.00 1 1 1 1 1 150 37.50 - Frequency is selected by hardware select, latched input; Spread controlled by pin - Frequency is selected by Bit 6:2; Spread controlled by bit 7 - SDRAM _OUT Disable - SDRAM _OUT Enable PWD 0 AGP 60.00 63.33 67.33 76.67 67.13 68.67 70.00 73.33 68.00 69.33 70.67 71.33 72.00 72.67 73.33 74.00 74.67 75.33 76.00 77.33 78.00 78.67 79.33 60.00 60.50 61.00 61.50 62.00 62.50 66.67 70.00 75.00 29
3,2, 6:4
Reserved Note1
1 0
0 1 0 1
0 1
Notes: 1. Default at power-up will be latched logic inputs to define frequency, as displayed by Bit 1. 2. PWD = Power-Up Default
Third party brands and names are the property of their respective owners.
8
ICS9248-110
I2C Command Bitmaps
Byte 4: Clock Control Register
Bit Pin# 7 1 6 23 5 22 4 20 3 19 2 42, 43 1 39, 40 0 36, 37 Default 1 1 1 1 1 1 1 1 Description REF0 enable 24MHz/48MHz enable USB0 enable AGP1 enable AGP0 enable CPUCLK2 enable (both of differential pair, True" and "Complimentary" CPUCLK1 enable (both of differential pair, True" and "Complimentary" CPUCLK0 enable (both of differential pair, True" and "Complimentary"
Notes: A value of '1'b is enable, '0'b is disable
Byte 5: PCI Clock Control Register
Bit 7 6 5 4 3 2 1 0 Pin# 2 17 16 14 13 11 10 8 Default 1 1 1 1 1 1 1 1 Description REF1 enable PCICLK6 enable PCICLK5 enable PCICLK4 enable PCICLK3 enable PCICLK2 enable PCICLK1 enable PCICLK0 enable
Notes: A value of '1'b is enable, '0'b is disable
Third party brands and names are the property of their respective owners.
9
ICS9248-110
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70 C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Input High Voltage VIH Input Low Voltage VIL Input High Current IIH VIN = VDD Input Low Current IIL1 VIN = 0 V; Inputs with no pull-up resistors Input Low Current IIL2 VIN = 0 V; Inputs with pull-up resistors CL =20 pF; Select @ 66 MHz IDD3.3OP CL =20 pF; Select @ 100 MHz Operating Supply Current CL = 20 pF; Select @ 133 MHz Power Down PD Input frequency Fi VDD = 3.3 V
Logic Inputs X1 & X2 pins 1 Clk Stabilization From VDD = 3.3 V to 1% target Freq. TCPU-SDRAM Vt=50% CPU - 1.5V SDRAM; CPU Leads TCPU-PCI Vt=50% CPU - 1.5V PCI; CPU Leads Skew1 TCPU-AGP Vt =50% CPU - 1.5V AGP; CPU Leads 1 Guaranteed by design, not 100% tested in production. Input Capacitance1 CIN CINX TSTAB MIN 2 VSS-0.3 MAX UNITS VDD+0.3 V 0.8 V 5 uA -5 uA -200 uA 87 160 mA 116 160 127 160 mA 600 uA 12 14.318 16 MHz 5 45 3 400 550 250 pF pF ms ps ps ps TYP
27 120 160 65
Third party brands and names are the property of their respective owners.
10
ICS9248-110
Electrical Characteristics - USB, REF
TA = 0 - 70C; VDD = 3.3V +/-5%; CL = 20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1
MIN 20 20 2.4
TYP 47 44
MAX UNITS 60 60 0.4 -22 V V mA mA ns ns % ps
RDSP2B
1 1
VO=VDD*(0.5) VO=VDD*(0.5) IOH = -12 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V
RDSN2B VOH5 VOL5 IOH5 IOL5 tr5 tf5
1 1 1
16 2.6 2.5 45 51 320 4.0 4.0 55 700
Duty Cycle REF Jitter, Cyl-to-Cyl
1
dt5
tjcyc-cyc5
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPUCLK (Open Drain)
TA = 0 - 70C; VDD=3.3V +/- 5%; CL = 20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Impedance Output High Voltage Output Low Voltage Output Low Current Rise Time Fall Time
1 1 1 1
MIN 1 18
TYP
MAX UNITS 60 1.8 0.8 V V mA ns ns V V V % ps ps ps
ZO VOH2B VOL2B IOL2B tr2B
1 1
1
VO=VX Termination to Vpull-up(external) Termination to Vpull-up(external) VOL = 0.3 V VOL = 20% , VOH = 80% VOH = 80%, VOL = 20% Note 2 Note 2 Note 3 VT = 50% VT = 50%
1
2.4 1.2 0.4 0.2 1.1 44
2.6 2.6
tf2B
Differential voltage-AC Diff Crossover Voltage Duty Cycle Skew window1 Jitter, Cycle-to-cycle1
1
VDIF VDIF VX dt2B
1 1
Vpull-up(ext) Vpull-up(ext) 1.4 46 40 80 1.7 54 200 250
Differential voltage-DC
1
tsk2B
tjcyc-cyc2B
V T = VX
VT = 50% tjabs2B1 120 250 Jitter, Absolute1 Notes: 1 - Guaranteed by design, not 100% tested in production. 2 - VDIF specifies the minimum input differential voltages (VTR-VCP) required for switching, where VTR is the "true" input Level and VCP is the "complement" input level. 3 - Vpull-up(external) = 2.7V, Min=Vpull-up(external)/2-150mV; Max=Vpull-up(external)/2 +150mV
Third party brands and names are the property of their respective owners.
11
ICS9248-110
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = VDDL = 3.3V +/-5%; CL = 30 pF (unles s otherwis e s pecified) PA RA M ETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Ris e Time Fall Time
1 1 1 1
SYM BOL RDSP 2 B
1 1
CONDITIONS VO=VDD*(0.5) VO=VDD*(0.5) IOH = -11 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
M IN 12 12 2.6
TYP 24 23
M A X UNITS 55 55 0.4 -16 V V mA mA ns ns % ps ps
RDSN2B VOH1 VOL1 IOH1 IOL1 tr1 tf1 dt1
19 1.65 1.60 45 50 300 70 2.5 2.5 55 400 200
Duty Cycle
Skew window
1
Jitter, Cyc-to-Cyc
tsk1 tjcyc-cyc1
Guaranteed by des ign, not 100% tes ted in production.
Electrical Characteristics - PCICLK_F
TA = 0 - 70C; VDD = 3.3V +/-5%; CL = 20 pF (unles s otherwis e s pecified) PA RA M ETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Ris e Time Fall Time
1 1 1 1
SYM BOL RDSP 2 B
1 1
CONDITIONS VO=VDD*(0.5) VO=VDD*(0.5) IOH = -11 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
M IN 12 12 2.6
TYP 24 23
M A X UNITS 55 55 0.4 -12 V V mA mA ns ns % ps ps
RDSN2B VOH1 VOL1 IOH1 IOL1 tr1 tf1 dt1
12 1.4 1.3 45 51 300 70 2.0 2.0 55 400 200
Duty Cycle
Skew window
1
Jitter, Cyc-to-Cyc
tsk1 tjcyc-cyc1
Guaranteed by des ign, not 100% tes ted in production.
Third party brands and names are the property of their respective owners.
12
ICS9248-110
Electrical Characteristics - AGP
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1
MIN 12 12 2
TYP
MAX UNITS 55 55 0.4 -19 V V mA mA ns ns % ps ps
RDSP4B
1 1
VO=VDD*(0.5) VO=VDD*(0.5) IOH = -18 mA IOL = 18 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
RDSN4B VOH4B VOL4B IOH4B IOL4B tr4B tf4B dt4B tsk1
19 1 1 45 50 50 288 2 2 55 200 450
Duty Cycle Skew window1 Jitter Cyc-Cyc
1
tjcyc-cyc1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM _OUT
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 30 pF (unles s otherwis e s pecified) PA RA M ETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current SD (0:1,3:12) Ris e Time SD(0:1,3:12) Fall Time
1 1 1
SYM BOL RDSP
1 1
CONDITIONS VO=VDD*(0.5) VO=VDD*(0.5) IOH = -11 mA IOL = 11 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V
M IN 12 12 2
TYP
M A X UNITS 55 55 0.4 -12 V V mA mA ns ns % ps
RDSN VOH3 VOL3 IOH1 IOL3 tr3 tf3
1 1 1
12 1 1 45 50 70 2 2 55 150
SD(0:1,3:12) Duty Cycle 1 Skew window
1
dt3 tsk
1
Guaranteed by des ign, not 100% tes ted in production.
Third party brands and names are the property of their respective owners.
13
ICS9248-110
SYMBOL
In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX 2.413 0.203 0.203 2.794 0.406 0.343 .095 .008 .008 .110 .016 .0135
A A1 b c D E E1 e h L N VARIATIONS N 48
0.127 0.254 SEE VARIATIONS 10.033 7.391 0.381 10.668 7.595 0.635
.005 .010 SEE VARIATIONS .395 .291 .015 .420 .299 .025
0.635 BASIC 0.508 1.016 SEE VARIATIONS 0 8
0.025 BASIC .020 .040 SEE VARIATIONS 0 8
D mm. MIN 15.748 MAX 16.002 MIN .620
D (inch) MAX .630
6/1/00 REV B
JEDEC MO-118 DOC# 10-0034
Ordering Information
ICS9248yF-110
Example:
ICS XXXX y F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
Third party brands and names are the property of their respective owners.
14
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

▲Up To Search▲

Price & Availability of ICS9248-110

	To Download ICS9248-110 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .