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CXP85452/85460
CMOS 8-bit Single Chip Microcomputer
Description The CXP85452/85460 are a highly integrated microcomputers composed of a 8-bit CPU, ROM, RAM, and I/O ports. These chips feature many other highperformance circuits in a single-chip CMOS design, including an A/D converter, serial interface, timer/counter, time-base timer, on-screen display function, I2C bus interface, PWM output, remote control reception circuit, HSYNC counter, and watchdog timer. Futhermore, the CXP85452/85460 series provides power-on reset and sleep functions which enable to lower power consumption. 64 pin SDIP (PIastic) 64 pin QFP (PIastic)
Structure Silicon gate CMOS IC
Features * A wide instruction set (213 instructions) which covers various types of data - 16-bit operation/multiplication and division/Boolean bit operation instructions * Minimum instruction cycle 0.5s at 8MHz * Incorporated ROM capacity 52K bytes (CXP85452) 60K bytes (CXP85460) * Incorporated RAM capacity 960 bytes * Peripheral functions - A/D converter 8-bit, 4-channel successive approximation method (Conversion time of 20s at 8MHz) - Serial interface 8-bit clock sync type, 1 channel - Timer 8-bit timer 8-bit timer/counter 19-bit time-base timer - On screen display (OSD) function 12 x 18 dots, 384 character types, 15 character colors, 12lines of 32 characters, black frame output/half blanking, shadow, background color on full screen/half blanking, double scanning, jitter elimination circuit - I2C bus interface - PWM output 14 bits, 1 channel 8 bits, 8 channels - Remote control reception circuit 8-bit pulse measurement circuit, 6-state FIFO - HSYNC counter 2 channels - Watchdog timer * Interruption 13 factors, 13 vectors, multi-interruption possible * Standby mode SLEEP * Package 64-pin plastic SDIP/QFP * Piggyback/evaluator CXP85400 64-pin ceramic PSDIP/PQFP CXP85490 64-pin ceramic PSDIP (accommodates custom font)
Purchase of Sony's I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E94323B86
Block Diagram
XTAL
VDD VSS
EXTAL RST MP
INT0 INT1 INT2
XLC EXLC R G B I YS YM HSYNC VSYNC
ON SCREEN DISPLAY
PORT A
2
SPC700 CPU CORE
CLOCK GENERATOR/ SYSTEM CONTROL
PA0 to PA7
INTERRUPT CONTROLLER
SI SO SCK ROM 52K/60K RAM 960 BYTES
SERIAL INTERFACE UNIT
HS0 WATCH DOG TIMER
HSYNC COUNTER 0 PRESCALER/ TIME BASE TIMER PE0 to PE5 PE6 to PE7
SCL0 SCL1 SDA0 SDA1 14 BIT PWM
I2C BUS INTERFACE UNIT
8 BIT PWM 8CH
PWM
PWM0 to PWM7
PORT F
AN0 to AN3
A/D CONVERTER
PORT E
HS1
HSYNC COUNTER 1
PORT D
-2-
FIFO
RMC
REMOCON
PORT C
EC TO
8 BIT TIMER/COUNTER 0
PORT B
2
PB0 to PB7
8 BIT TIMER 1
PC0 to PC7
PD0 to PD7
PF0 to PF7
CXP85452/85460
CXP85452/85460
Pin Assignment (Top View) 64-pin SDIP
HSYNC/PA7 VSYNC/PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 EC/PD7 RMC/PD6 HS1/PD5 HS0/PD4 SI/PD3 SO/PD2 SCK/PD1 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VDD NC VSS MP PF0/PWM0 PF1/PWM1 PF2/PWM2 PF3/PWM3 PF4/PWM4/SCL0 PF5/PWM5/SCL1 PF6/PWM6/SDA0 PF7/PWM7/SDA1 YM YS I B G R EXLC XLC PE0/INT0 PE1/INT1 AN0/PE2 AN1/PE3 AN2/PE4 AN3/PE5 PE6/PWM PE7/TO RST EXTAL XTAL PD0/INT2
Note) 1. NC (Pin 63) is always connected to VDD. 2. Vss (Pins 32 and 62) are both connected to GND. 3. MP (Pin 61) is always connected to GND.
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CXP85452/85460
Pin Assignment (Top View) 64-pin QFP
PA6/VSYNC
PA7/HSYNC
PA4
VSS
64 63 62 61 60 59 58 57 56 55 54 53 52 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 EC/PD7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PF3/PWM3 PF4/PWM4/SCL0 PF5/PWM5/SCL1 PF6/PWM6/SDA0 PF7/PWM7/SDA1 YM YS I B G R EXLC XLC PE0/INT0 PE1/INT1 AN0/PE2 AN1/PE3 AN2/PE4 AN3/PE5
INT2/PD0
PF0/PWM0
PA2
HS1/PD5
TO/PE7
PF1/PWM1
PA3
VDD
NC
MP
Note) 1. NC (Pin 56) is always connected to VDD. 2. Vss (Pins 26 and 58) are both connected to GND. 3. MP (Pin 55) is always connected to GND.
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PWM/PE6
SO/PD2
XTAL
RMC/PD6
HS0/PD4
SI/PD3
SCK/PD1
EXTAL
RST
VSS
PF2/PWM2
PA5
CXP85452/85460
Pin Description Symbol PA0 to PA5 PA6/VSYNC PA7/HSYNC PB0 to PB7 I/O I/O/Input I/O/Input I/O I/O Description (Port A) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) OSD display vertical synchronization signal input pin. OSD display horizontal synchronization signal input pin. (Port B) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) Input pin for external interruption request. Active when falling edge. (Port D) 8-bit I/O port. I/O can be set in a unit of single bits. 12mA sink current drive possible. (8 pins) Serial clock I/O pin. Serial data output pin. Serial data input pin. HSYNC counter (CH0) input pin. HSYNC counter (CH1) input pin. Remote control reception circuit input pin. External event input pin for timer/counter. Input pin for external interruption request. Active when falling edge. (2 pins) (Port E) 8-bit port. Lower 6 bits are for inputs; upper 2 bits are for outputs. (8 pins) Analog input pin for A/D converter. (4 pins) 14-bit PWM output pin. (CMOS output) Timer/counter rectangular wave output pin. (Port F) 8-bit output port. Large current (12mA) N-ch open drain output. Lower 4 bits are mid-voltage drive (12V); upper 4 bits are 5V drive. (8 pins) 8-bit PWM output pin. (8 pins)
PC0 to PC7
I/O
PD0/INT2 PD1/SCK PD2/SO PD3/SI PD4/HS0 PD5/HS1 PD6/RMC PD7/EC PE0/INT0 PE1/INT1 PE2/AN0 to PE5/AN3 PE6/PWM PE7/TO PF0/PWM0 to PF3/PWM3 PF4/PWM4/ SCL0 PF5/PWM5/ SCL1 PF6/PWM6/ SDA0 PF7/PWM7/ SDA1
I/O/Input I/O/I/O I/O/Output I/O/Input I/O/Input I/O/Input I/O/Input I/O/Input Input/Input
Input/Input
Output/Output Output/Output Output/Output
Output/Output/ I/O
I2C bus interface transfer clock I/O pin. (2 pins)
Output/Output/ I/O
I2C bus interface transfer data I/O pin. (2 pins)
R, G, B, I, YS, YM Output
OSD display 6-bit output pin. (6 pins)
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CXP85452/85460
Symbol EXLC XLC EXTAL XTAL RST MP NC VDD Vss Input
I/O
Description OSD display clock oscillation I/O pin. Oscillation frequency is determined by the external L and C. Crystal connection pin for system clock oscillation. When using an external clock, input to EXTAL pin and leave XTAL pin open. System reset pin for active at low level. This pin becomes I/O pin, and outputs low level at the power on with power-on reset function executed. (Mask option) Test mode input pin. Always connect to GND. NC. Under normal operation, connect to VDD. Positive supply voltage pin. GND. Both Vss pins should be connected to common GND.
Output Input Output I/O Input
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CXP85452/85460
Input/Output Circuit Formats for Pins Pin Port A Port B Port C PA0 to PA5 PB0 to PB7 PC0 to PC7
Ports A, B, C data
Circuit format
When reset
Ports A, B, C direction "0" when reset IP Data bus RD (Ports A, B, C) Input protection circuit
Hi-Z
22 pins Port A
Port A data Port A direction "0" when reset
PA6/VSYNC PA7/HSYNC
Data bus RD (Port A) Schmitt input VSYNC HSYNC Input multiplexer
IP
Hi-Z
2 pins Port D PD0/INT2 PD3/SI PD4/HS0 PD5/HS1 PD6/RMC PD7/EC
Data bus RD (Port D) INT2, SI, HS0, HS1, RMC, EC
"0" when reset
Port D data Port D direction "0" when reset
Hi-Z
Schmitt input IP
Large current 12mA
6 pins
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CXP85452/85460
Pin Port D
SCK or SO Output enable
Circuit format
When reset
PD1/SCK PD2/SO
Port D data Port D direction "0" when reset Schmitt input
IP
Hi-Z
Data bus RD (Port D) SCK only
Large current 12mA
2 pins Port E PE0/INT0 PE1/INT1 2 pins Port E
Input multiplexer IP Schmitt input (Interrupt circuit)
Hi-Z
Data bus RD (Port E)
PE2/AN0 to PE5/AN3
IP
To A/D converter
Hi-Z
Port E function selection Data bus RD (Port E)
4 pins Port E
"0" when reset
TO, PWM
PE6/PWM PE7/TO
Port E data "1" when reset Port E function selection "1" when reset
High level
2 pins
-8-
CXP85452/85460
Pin Port F PF0/PWM0 to PF3/PWM3
PWM
Circuit format
When reset
Port F data "1" when reset Port F selection 12V voltage drive Large current 12mA
Hi-Z
4 pins Port F
"0" when reset
SCL, SDA
PF4/PWM4/ SCL0 PF5/PWM5/ SCL1 PF6/PWM6/ SDA0 PF7/PWM7/ SDA1
I2C output enable PWM
Hi-Z
Port F data "1" when reset Port F function selection "0" when reset Schmitt input BUS SW To internal I2C pins Large current 12mA IP
4 pins
SCL, SDA (I2C circuit)
R G B I YS YM 6 pins
R, G, B, I, YS, YM
Output polarity "0" when reset Writing data to output polarity register brings output to active
Hi-Z
EXLC XLC
EXLC
IP
Oscillator control
Oscillation halted
XLC IP OSD display clock
2 pins
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CXP85452/85460
Pin
Circuit format
When reset
EXTAL XTAL
* Shows the circuit composition during oscillation. EXTAL IP * Feedback resistor is removed during STOP. (This device does not enter the STOP mode.) XTAL
Oscillation
2 pins
Pull-up resistor Mask option
RST
Schmitt input
OP
Low level
From power-on reset circuit (Mask option)
1 pin
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CXP85452/85460
Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage Mid-voltage drive output voltage High level output current High level total output current Symbol VDD VIN VOUT VOUTP IOH IOH IOL Low level output current IOLC Low level total output current Operating temperature Storage temperature Allowable power dissipation IOL Topr Tstg PD 20 130 -20 to +75 -55 to +150 1000 600 mA mA C C mW mW SDIP QFP Ratings -0.3 to +7.0 -0.3 to +7.01 -0.3 to +7.01 -0.3 to +15.0 -5 -50 15 Unit V V V V mA mA mA
(Vss = 0V reference) Remarks
PF0 to PF3 pins
Total of all output pins Ports excluding large current output (value per pin) Large current output port (value per pin)2 Total of all output pins
1 VIN and VOUT should not exceed VDD + 0.3V. 2 The large current output port is Port D (PD) and Port F (PF). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should better take place under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI. Recommended Operating Conditions Item Symbol Min. 4.5 Supply voltage VDD 3.5 2.5 VIH High level input voltage VIHS VIHEX VIL Low level input voltage VILS VILEX Operating temperature Topr 1 2 3 4 0.7VDD 0.8VDD VDD - 0.4 0 0 -0.3 -20 Max. 5.5 5.5 5.5 VDD VDD VDD + 0.3 0.3VDD 0.2VDD 0.4 +75 Unit V V V V V V V V V C (Vss = 0V reference) Remarks Guaranteed operation range for 1/2 and 1/4 frequency dividing modes. Guaranteed operation range for 1/16 frequency dividing mode or SLEEP mode. Guaranteed data hold range for STOP mode.1 2 3 EXTAL pin4 2 3 EXTAL pin4
This device does not enter the STOP mode. PA, PB, PC, PE2 to PE5, SCL0, SCL1, SDA0, SDA1 pins INT2, SCK, SI, HS0, HS1, RMC, EC, INT0, INT1, HSYNC, VSYNC, RST pins Specifies only during external clock input.
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CXP85452/85460
DC Characteristics Item High level output voltage Symbol VOH Pin
(Ta = -20 to +75C, Vss = 0V reference) Condition Min. 4.0 3.5 0.4 0.6 1.5 0.4 0.6 0.5 -0.5 -1.5 40 -40 -400 10 50 10 120 Typ. Max. Unit V V V V V V V A A A A A A
PA to PD, PE6, PE7, VDD = 4.5V, IOH = -0.5mA R, G, B, I, YS, YM VDD = 4.5V, IOH = -1.2mA PA to PD, PE6, PE7, VDD = 4.5V, IOL = 1.8mA R, G, B, I, YS, YM, PF0 to PF3, RST1 VDD = 4.5V, IOL = 3.6mA
Low level output voltage
VOL
PD, PF PF4 to PF7 (SCL0, SCL1, SDA0, SDA1)
VDD = 4.5V, IOL = 12.0mA VDD = 4.5V, IOL = 3.0mA VDD = 4.5V, IOL = 4.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V
IIHE Input current IIHL IILR I/O leakage current Open drain output leakage current (N-ch Tr off) IIZ
EXTAL RST2 PA to PE, HSYNC, VSYNC, R, G, B, I, YS, YM, RST2 PF0 to PF3
VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VI = 0, 5.5V VDD = 5.5V, VOH = 12.0V VDD = 5.5V, VOH = 5.5V VDD = 4.5V VSCL0 = VSCL1 = 2.25V VSDA0 = VSDA1 = 2.25V 1/2 frequency dividing operation mode VDD = 5.5V, 8MHz crystal oscillation (C1 = C2 = 22pF)
ILOH PF4 to PF7 SCL0: SCL1 SDA0: SDA1
I2C bus switch connection impedance RBS (Output Tr off)
IDD
18
30
mA
Supply current
IDDSL
VDD3
SLEEP mode VDD = 5.5V, 8MHz crystal oscillation (C1 = C2 = 22pF) STOP mode4 VDD = 5.5V, termination of 8MHz oscillation
0.9
3
mA
IDDST
--
--
--
A
Input capacitance
CIN
PA to PD, PE0 to PE5, SCL, SDA, EXLC, EXTAL, RST
1MHz clock 0V for non-measurement pins
10
20
pF
1 Specifies RST pin only when the power-on reset circuit is selected with mask option. 2 For RST pin, specifies the input current when pull-up resistor is selected, and specifies the leakage current when non-resistor is selected. 3 When all output pins open. Specifies only when the OSD oscillation is halted. 4 This device does not enter the stop mode.
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CXP85452/85460
AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock rise and fall times Event count input clock pulse width Event count input clock rise and fall times 1 Symbol fC Pin XTAL EXTAL EXTAL EXTAL EC EC
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Fig. 1, Fig. 2 Fig. 1, Fig. 2 External clock drive Fig 1, Fig 2 External clock drive Fig. 3 Fig. 3 Min. 3.5 Max. 9 Unit MHz ns ns ns 20 ms
tXL, tXH tCR, tCF tEH, tEL tER, tEF
50 200
tsys + 501
tsys indicates three values according to the contents of the clock control register (CLC: 00FEH) upper 2 bits
(CPU clock selection). tsys (ns) = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Fig. 1. Clock timing
1/fc
VDD - 0.4V EXTAL 0.4V
tXH
tCF
tXL
tCR
Fig. 2. Clock applied condition
Crystal oscillation Ceramic oscillation
External clock
EXTAL
XTAL
EXTAL
XTAL
C1
C2
OPEN
Fig. 3. Event count clock timing
0.8VDD EC 0.2VDD
tEH
tEF
tEL
tER
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CXP85452/85460
(2) Serial transfer Item SCK cycle time SCK high and low level widths SI input set-up time (for SCK ) SI hold time (for SCK ) SCK SO delay time Symbol Pin SCK
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Input mode Output mode SCK SCK input mode SCK output mode SI SCK input mode SCK output mode SI SCK input mode SCK output mode SO SCK input mode SCK output mode Min. 1000 8000/fc 400 4000/fc - 50 100 200 200 100 200 100 Max. Unit ns ns ns ns ns ns ns ns ns ns
tKCY tKH tKL tSIK tKSI tKSO
Note) The load of SCK output mode and SO output delay time is 50pF + 1TTL.
Fig. 4. Serial transfer timing
tKCY tKL tKH
0.8VDD SCK 0.2VDD
tSIK
tKSI
0.8VDD SI Input data 0.2VDD
tKSO
0.8VDD SO 0.2VDD Output data
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CXP85452/85460
(3) A/D converter characteristics Item Resolution Linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling time Analog input voltage VZT1 VFT2 Symbol Pin
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Min. Typ. Max. 8 3 Ta = 25C VDD = 5.0V Vss = 0V -50 4910 160/fADC3 12/fADC3 AN0 to AN3 0 VDD 10 4970 70 5030 Unit Bits LSB mV mV s s V
tCONV tSAMP
VIAN
Fig. 5. Definitions for A/D converter terms
FFH FEH
Digital conversion value
1 VZT: Digital conversion values change between 00H 01H. 2 VFT: Digital conversion values change between 0EH 0FH. 3 fADC indicates the below values due to the contents of bit 6 (CKS) of the A/D control registor (ADC: 00F6H) and the bits 7 (PCK1) and 6 (PCK0) of the clock control registor (CLC: 00FEH)
Linearity error
CKS PCK1, 0 00 ( = fEX/2)
0 (/2 selection) fADC = fC/2 fADC = fC/4 fADC = fC/16
1 ( selection) fADC = fC fADC = fC/2 fADC = fC/8
01H 00H
VZT Analog input
VFT
01 ( = fEX/4) 11 ( = fEX/16)
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CXP85452/85460
(4) Interruption, reset input (Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item External interruption high and low level widths Reset input low level width Symbol Pin INT0 to INT2 RST Condition Min. 1 8/fc Max. Unit s s
tIH tIL tRSL
Fig. 6. Interruption input timing
tIH tIL
INT0 to INT2 (falling edge)
0.8VDD 0.2VDD
Fig. 7. RST input timing
tRSL
RST 0.2VDD
(5) Power-on reset Power-on reset1 Item Power supply rise time Power supply cutt-off time Symbol
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Pin VDD Condition Power-on reset Repeated power-on reset Min. 0.05 1 Max. 50 Unit ms ms
tR tOFF
1 Specifies only when power-on reset function is selected. Fig. 8. Power-on reset
4.5V VDD 0.2V tR Take care when turning on power. tOFF 0.2V
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CXP85452/85460
(6) I2C bus timing Item SCL clock frequency Bus-free time before starting transfer Hold time for starting transfer Clock low level width Clock high level width Set-up time for repeated transfers Data hold time Data set-up time SDA, SCL rise time SDA, SCL fall time Set-up time for transfer completion
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol fSLC Pin SCL SDA, SCL SDA, SCL SCL SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL 4.7 Condition Min. 0 4.7 4.0 4.7 4.0 4.7 01 250 1 300 Max. 100 Unit kHz s s s s s s ns s ns s
tBUF tHD; STA tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tR tF tSU; STO
1 For the data hold time, the SCL rise time (300ns Max.) is not considered so that 300ns should be exceeded.
Fig. 9. I2C bus transfer data timing
SDA tBUF tR SCL tHD; STA P S tLOW tHD; DAT tHIGH tSU; DAT St tSU; STA tSU; STO P tF tHD; STA
Fig. 10. I2C device recommended circuit
I2C device RS SDA0 (or SDA1) SCL0 (or SCL1) RS RS
I2C device RS RP RP
* A pull-up resistor (Rp) must be connected to SDA0 (or SDA1), and SCL0 (or SCL1). * The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance (Rs = 300 or less) can be used to reduce spike noise caused by CRT flashover.
- 17 -
CXP85452/85460
(7) OSD timing Item OSD clock frequency HSYNC pulse width VSYNC pulse width HSYNC afterwrite rise and fall times VSYNC beforewrite rise and fall times
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol fOSC Pin EXLC XLC HSYNC HSYNC HSYNC VSYNC Condiiton Fig. 12 Fig. 11 Fig. 11 Fig. 11 Fig. 11 Min. 4 1.2 1 200 1.0 Max. 71 142 Unit MHz s H3 ns s
tHWD tVWD tHCG tVCG
1 Oscillation clock at 4MHz operation 2 Oscillation clock at 8MHz operation 3 H indicates 1HSYNC period. Fig. 11. OSD timing
tHWD tHCG
HSYNC For OSD I/O polarity register (OPOL: 01FAH) bit 7 at "0"
0.8VDD
0.2VDD
tVCG
tVWD 0.8VDD
VSYNC For OSD I/O polarity register (OPOL: 01FAH) bit 6 at "0"
0.2VDD
Fig. 12. LC oscillation circuit connection
EXLC
XLC R1
L
C1
C2
1 The series resistor for XLC is used to reduce the frequency of occurrence of the undesired radiation.
- 18 -
CXP85452/85460
Appendix Fig. 13. SPC700 Series recommended oscillation circuit (i) (ii)
EXTAL
XTAL Rd
EXTAL
XTAL Rd
C1
C2 C1 C2
Manufacturer
Model CSA4.00MG CSA4.19MG
fc (MHz) 4.00 4.19 8.00 4.00 4.19 8.00 4.00
C1 (pF)
C2 (pF)
Rd ()
Circuit Example
(i) 30 30 02 (ii)
MURATA MFG CO., LTD.
CSA8.00MTZ CST4.00MGW1 CST4.19MGW1 CST8.00MTW1
RIVER ELETEC CO., LTD.
HC-49/U03
4.19 8.00 4.00
12
12
02
(i)
KINSEKI LTD.
HC-49/U(-S)
4.19 8.00
27
27
02
(i)
1 These models have the on-chip grounding capacitors (C1 and C2). 2 The series resistor for XTAL can reduce the effect of the noise caused by the electrostatic discharge.
Mask Option Table Item Reset pin pull-up resistor Power-on reset circuit Inclusion Non-existent Non-existent Existent Existent
- 19 -
CXP85452/85460
Fig. 14. Characteristics curves
IDD vs. VDD (fc = 8MHz, Ta = 25C, Typical)
IDD vs. fc (VDD = 5V, Ta = 25C, Typical)
10
20 1 2 frequency mode 1 frequency mode 18 4 16
1 2
frequency mode
IDD - Supply current [mA]
1 16 frequency mode
14
IDD - Supply current [mA]
SLEEP mode 1
12
10 1 4 8 frequency mode
6 0.1 2 3 4 5 6
4 1 frequency mode 16 2 SLEEP mode 0 1 5 10
VDD - Supply voltage [V]
fc - System clock [MHz]
Parameter Curve for OSD Oscillator L vs. C (Analytically calculated value)
100
5.0MHz
L - Inductance [H]
10
6.5MHz
13.0MHz fOSC = 1 2 LC C = C1 // C2
0 50 C1, C2 - Capacitance [pF] 100
- 20 -
CXP85452/85460
Package Outline
Unit: mm
64PIN SDIP (PLASTIC) 750mil
+ 0.4 57.6 - 0.1 64 33
19.05 + 0.3 17.1 - 0.1
+ 0.1 0.05 0.25 -
0 to 15 32 0.5 0.1 0.9 0.15
1 1.778
PACKAGE STRUCTURE
MOLDING COMPOUND SONY CODE EIAJ CODE JEDEC CODE SDIP-64P-01 SDIP064-P-0750-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY / PHENOL RESIN SOLDER PLATING 42 ALLOY 8.6g
64PIN QFP(PLASTIC)
23.9 0.4 + 0.4 20.0 - 0.1
51 33
3 MIN
0.5 MIN + 0.4 4.75 - 0.1
+ 0.1 0.15 - 0.05 0.15
52
32
17.9 0.4
+ 0.4 14.0 - 0.1
64
20
+ 0.2 0.1 - 0.05
1 1.0 + 0.15 0.4 - 0.1
19 + 0.35 2.75 - 0.15 0.12 M
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-64P-L01 QFP064-P-1420 LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER/PALLADIUM PLATING COPPER /42 ALLOY 1.5g
- 21 -
0.8 0.2
16.3

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Price & Availability of CXP85452

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