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| CXA2079Q S2-Compatible 6-Input 2-Output Audio/Video Switch Description The CXA2079Q is a 6-input, 2-output audio/video switch featuring I2C bus compatibility for TVs. This IC has input pins that are compatible with S2 protocol. Features * 4 inputs that are compatible with S2 protocol * Serial control with I2C bus * 6 inputs, 2 outputs * The desired inputs can be selected independently for each of the 2 outputs * Wide band video amplifier (20MHz, -3dB) * Y/C MIX circuit * Slave address can be changed (90H/92H) * Audio muting from external pin * High impedance maintained by I2C bus lines (SDA, SCL) even when power is OFF * Wide audio dynamic range (3Vrms typ.) Applications Audio/video switch featuring I2C bus compatibility for TVs Structure Bipolar silicon monolithic IC 64 pin QFP (Plastic) Absolute Maximum Ratings * Supply voltage VCC * Operating temperature Topr * Storage temperature Tstg * Allowable power dissipation PD Operating Conditions Supply voltage 12 -20 to +75 -65 to +150 1300 V C C mW 9 0.5 V Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E97430A7Y CXA2079Q Block Diagram TV 63 V1 V2 1 8 6dB 6dB 53 VOUT1 49 YIN1 56 YOUT1 55 TRAP1 V3 15 V4 22 V5 60 6dB Y1 3 Y2 10 Y3 17 Y4 24 6dB 6dB 58 COUT1 51 CIN1 41 VOUT2 45 YIN2 39 YOUT2 C1 5 6dB C2 12 C3 19 C4 26 BIAS 37 COUT2 43 CIN2 57 VGND 50 BIAS 42 VCC 35 AGND LTV 62 LV1 2 6dB 0dB 44 AGND2 52 LOUT1 LV2 9 LV3 16 LV4 23 LV5 59 6dB RTV 64 RV1 4 6dB 0dB 38 LOUT2 54 ROUT1 6dB 40 ROUT2 36 DC OUT 33 SCL 34 SDA 32 ADR 7 S-1 RV2 11 RV3 18 RV4 25 RV5 61 Logic 14 S-2 21 S-3 28 S-4 NC 29 NC 30 NC 31 NC 46 NC 47 6 S2-1 13 S2-2 20 S2-3 27 S2-4 48 MUTE Audio system is attenuated by 6dB for 6k resistor input, and a total gain is 0dB (LOUT1 and ROUT1 can be changed to -6dB). -2- CXA2079Q Pin Configuration AGND2 LOUT2 COUT2 DC OUT ROUT2 VOUT2 YOUT2 MUTE BIAS YIN1 CIN2 AGND CIN1 YIN2 SDA 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VCC NC NC SCL 32 LOUT1 52 VOUT1 53 ROUT1 54 TRAP1 55 YOUT1 56 VGND 57 COUT1 58 LV5 59 V5 60 RV5 61 LTV 62 TV 63 RTV 64 ADR 31 NC 30 29 NC NC 28 S-4 27 S2-4 26 C4 25 RV4 24 Y4 23 LV4 22 V4 21 S-3 20 S2-3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 S2-2 S-1 V1 S2-1 RV2 RV1 RV3 C2 C1 LV2 LV1 LV3 Y2 Y1 S-2 V2 V3 Y3 -3- C3 CXA2079Q Pin Description Pin No. Symbol Pin voltage Equivalent circuit Description 63 1 8 15 22 60 TV V1 V2 V3 V4 V5 VCC 63 15 150 3A 4.0V 1 8 22 60 Video signal inputs. Input composite video signals. 3 10 17 24 49 45 Y1 Y2 Y3 Y4 YIN1 YIN2 3 10 VCC 150 3A 4.0V 17 24 49 45 Y/C separation signal inputs. Input luminance signals. The YIN1 pin inputs the signal obtained by Y/C separating the VOUT1 pin output. The YIN2 pin inputs the signal obtained by Y/C separating the VOUT2 pin output. Y/C separation signal inputs. Input chrominance signals. The CIN1 pin inputs the signal obtained by Y/C separating the VOUT1 pin output. The CIN2 pin inputs the signal obtained by Y/C separating the VOUT2 pin output. 5 12 19 26 51 43 C1 C2 C3 C4 CIN1 CIN2 5 12 VCC 20k 150 27k 4.5V 19 26 51 43 62 2 9 16 23 59 64 4 11 18 25 61 LTV LV1 LV2 LV3 LV4 LV5 RTV RV1 RV2 RV3 RV4 RV5 62 64 2 4 VCC 33k 27k 4.5V 9 11 16 18 23 25 59 61 15k Audio signal inputs. VCC 250 VCC 53 41 VOUT1 VOUT2 3.9V 53 41 30k 27k 23.5k Video signal outputs. Output composite video signals. -4- CXA2079Q Pin No. Symbol Pin voltage Equivalent circuit VCC VCC VCC VCC Description 56 39 YOUT1 YOUT2 3.3V 56 39 Video signal outputs. Output luminance signals. VCC VCC VCC VCC 58 37 COUT1 COUT2 4.5V 58 37 Video signal outputs. Output chrominance signals. VCC VCC 56 20k 20k 52 38 54 40 LOUT1 LOUT2 ROUT1 ROUT2 52 4.5V 38 54 40 Audio signal outputs. Zo = 50 (within DC 2mA) VCC VCC 6 13 20 27 S2-1 S2-2 S2-3 S2-4 6 VCC 147 100k -- 13 20 27 Detects the S2-compatible DC superimposed onto the C signal. 4:3 video signal at 1.3V or less 4:3 letter-box signal at 1.3V or more to 2.5V or less 16:9 picture squeezed signal at 2.5V or more These pins are pulled down to GND by a 100k resistor, so the 4:3 video signals are selected when open. Composite video/S selector. The detection results are written to the status register. S signal at 3.5V or less Composite video signal at 3.5V or more These pins are pulled up to 5V by a 100k resistor, so the composite video signals are selected when open. Selects the slave address for the I2C bus. 90H at 1.5V or less 92H at 2.5V or more 90H when open 5V 7 14 21 28 S-1 S-2 S-3 S-4 7 -- VCC 100k 50k VCC 50k VCC 14 21 28 10k VCC 147 32 28k 72k 32 ADR -- -5- CXA2079Q Pin No. Symbol Pin voltage Equivalent circuit VCC Description 33 SCL -- 4k 33 10k I2C bus signal input VILmax = 1.5V VIHmin = 3.0V VCC 34 SDA -- 34 4k I2C bus signal input VILmax = 1.5V VIHmin = 3.0V VOLmax = 0.4V VCC 4k 36 28k 1k 36 DC OUT -- Q1 Outputs the S2-compatible DC superimposed onto the COUT2 output. The DC is superimposed by connecting this pin to the COUT2 output via a capacitor. Control is performed by the I2C bus. When 0V is output, Q1 is ON and the impedance is 5k. S2 protocol output DC impedance of 10 3k is realized by attaching external resistance of 4.7k. DC OUT (bus) Output DC 0 4.5V 1 0V 2 1.9V 3 4.5V VCC 100 55 TRAP1 3.8V 55 1k Connects trap circuit for subcarrier. VCC 147 48 28k 72k 48 MUTE -- Audio signal output mute. Mute OFF at 1.5V or less Mute ON at 2.5V or more Mute OFF when open VCC VCC VCC 147 50 BIAS 4.5V 20k 50 20k Internal reference bias (Vcc/2). Connects to GND via a capacitor. -6- CXA2079Q Electrical Characteristics Item Current consumption Symbol ICC Conditions No signal, no load Min. 30 (Ta = 25C, VCC = 9V) Typ. 45 Max. 62 Unit mA Video system (Measurement circuit; Fig. 1) Gain Frequency response characteristics Frequency response characteristics (Y/C mix) Input dynamic range Cross talk GVv FBWv1 f = 100kHz, 0.3Vp-p input f = 100kHz, input frequency where output amplitude is -3dB with 0.3Vp-p output serving as 0dB f = 100kHz, maximum with distortion < 1.0% f = 4.43MHz, 1Vp-p input 5.9 15 6.4 20 6.9 -- dB MHz FBWv2 10 15 -- MHz Ddv Vctv 1.4 -- -- -- -- -50 Vp-p dB Audio system (Measurement circuits; Fig. 2 to Fig. 5) Gain Frequency response characteristics Total harmonic distortion Input dynamic range Cross talk Ripple rejection ratio Output DC offset Residual noise GVA f = 1kHz, 1Vp-p input, 5.7k resistor inserted to input f = 1kHz, input frequency where output amplitude is -3dB with 1Vp-p output serving as 0dB f=1kHz, 2.2Vp-p input, where 400Hz HPF + 80kHz LPF are inserted f=1kHz, maximum with distortion < 0.3% f=1kHz, 1Vp-p input f=100Hz, 0.3Vp-p applied to Vcc Offset voltage between input and output When 400Hz HPF+ 30kHz LPF are inserted f=1kHz, 1Vrms input When 400Hz HPF + 30kHz LPF are inserted -1 0 1 dB FBWA 50 -- -- kHz THD DdA VctA VctA Voff VNA -- 2.8 -- -- -30 0 0.03 3.0 -90 -55 -- 20 0.05 -- -80 -40 30 30 % Vrms dB dB mV Vrms S/N ratio S/N -100 -90 dB -7- CXA2079Q Logic system Item High level input voltage Low level input voltage Symbol VIH VIL With SDA 3mA current supplied VIH = 4.5V VIL = 0.4V Conditions Min. 3.0 0 0 0 0 0 4.7 4.0 4.7 4.0 4.7 0 250 -- -- 4.7 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 5.0 1.5 0.4 10 10 100 -- -- -- -- -- -- -- 1 300 -- Unit V V V A A kHz s s s s s ns ns s ns s Low level output voltage VOL High level input current Low level input current Maximum clock frequency Minimum waiting time for data change Minimum waiting time for data transfer start Low level clock pulse width High level clock pulse width Minimum waiting time for start preparation Minimum data hold time Minimum data preparation time Rise time Fall time Minimum waiting time for stop preparation IIH IIL fSCL tBUF tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tR tF tSU;STO -8- Measurement point 75 10 0.47 22 42 34 41 40 39 38 36 33 37 35 50 47 44 49 48 45 43 46 0.47 0.1 10 10 -com 1k 10k 10 10k 10 10k 10 75 75 75 10k 10k 0.1 51 NC NC VCC YIN1 YIN2 CIN1 BIAS CIN2 SDA SCL ADR NC 31 NC 30 NC 29 S-4 28 S2-4 27 0.1 C4 26 1 RV4 25 0.47 Y4 24 1 LV4 23 0.47 V4 22 S-3 21 S2-3 20 75 600 75 600 75 32 19 0.1 75 10k 10 MUTE VOUT2 YOUT2 LOUT2 AGND2 10k 10 53 VOUT1 10k 10 54 ROUT1 55 TRAP1 10k 10 56 YOUT1 57 VGND 10k 10 58 COUT1 600 1 59 LV5 LV1 RV1 S2-1 V2 Y2 C2 S-2 LV3 RV3 RV2 11 12 0.1 13 V1 Y1 C1 S-1 LV2 S2-2 V3 Y3 1 2 3 0.47 1 75 75 600 600 75 600 1 1 75 0.1 0.47 0.47 7 4 8 10 5 6 9 14 1 75 600 75 15 0.47 1 16 17 0.47 1 75 600 600 18 0.47 75 Input signal Signal is input from one of the following pins: 1, 3, 5, 8, 10, 12, 15, 17, 19, 22, 24, 26, 60 and 63. Output signal is measured from one of the following pins: 37, 39, 41, 53, 56 and 58. CXA2079Q Fig. 1. Video system (gain, frequency response characteristics, input dynamic range, cross talk) measurement circuit C3 -9- 75 0.47 60 V5 600 1 61 RV5 600 1 62 LTV 75 0.47 63 TV 600 1 64 RTV DC OUT AGND LOUT1 ROUT2 COUT2 52 Measurement point 75 10 0.47 22 41 34 40 39 38 36 33 37 35 50 47 44 42 49 48 45 43 46 0.47 0.1 10 10 10 -com 1k 10k 10 10k 10 75 75 75 10k 10k 10k 0.1 51 VCC BIAS YIN1 YIN2 CIN1 CIN2 SDA SCL ADR NC 31 NC 30 NC 29 S-4 28 S2-4 27 0.1 C4 26 5.7k 1 RV4 25 0.47 Y4 24 5.7k 1 LV4 23 0.47 V4 22 S-3 21 S2-3 20 75 600 75 600 75 32 19 10k MUTE ROUT2 AGND2 COUT2 10k 10 53 VOUT1 10k 10 54 ROUT1 55 TRAP1 10k 10 56 YOUT1 57 VGND 10k 10 58 COUT1 600 1 5.7k 59 LV5 LV1 RV1 S2-1 V2 V1 Y1 C1 S-1 LV2 RV2 S2-2 V3 Y3 Y2 C2 1 2 3 0.47 0.1 1 600 600 75 1 75 75 1 0.47 75 600 5.7k 5.7k 0.47 7 5.7k 4 8 5 6 9 10 11 5.7k 12 13 0.1 1 75 600 S-2 LV3 14 0.47 75 15 16 17 5.7k 0.47 1 75 600 18 5.7k 0.47 RV3 C3 0.1 1 75 600 - 10 - 75 0.47 60 V5 600 1 5.7k 61 RV5 600 1 5.7k 62 LTV 75 0.47 63 TV 600 1 5.7k 64 RTV 75 Input signal Signal is input from one of the following pins: 2, 4, 9, 11, 16, 18, 23, 25, 59, 61, 62 and 64. Output signal is measured from one of the following pins: 38, 40, 52 and 54. CXA2079Q Fig. 2. Audio system (gain, frequency response characteristics, total harmonic distortion, input dynamic range, cross talk) measurement circuit DC OUT LOUT1 VOUT2 YOUT2 LOUT2 AGND 52 NC NC 10 Measurement point 75 75 75 -com 36 34 33 35 1k 0.47 0.1 45 44 42 41 39 38 43 40 37 48 47 46 10 10 10 49 75 10k 10k 10k 0.1 10 51 50 VCC BIAS YIN1 YIN2 CIN1 CIN2 SDA SCL ADR NC 31 NC 30 NC 29 S-4 28 S2-4 27 0.1 C4 26 1 RV4 25 0.47 Y4 24 1 LV4 23 0.47 V4 22 S-3 21 S2-3 20 75 600 75 600 75 32 19 10k MUTE ROUT2 VOUT2 YOUT2 LOUT2 10k 10 53 VOUT1 10k 10 54 ROUT1 55 TRAP1 10k 10 56 YOUT1 57 VGND 10k 10 LV1 RV1 S2-1 V2 Y2 C2 S-2 LV3 RV3 RV2 11 1 12 13 V1 Y1 C1 S-1 LV2 S2-2 V3 Y3 1 3 0.47 1 0.47 75 600 1 75 75 600 75 0.1 4 7 8 2 5 6 9 10 14 0.1 600 75 15 0.47 75 1 600 16 17 0.47 1 75 600 18 0.47 0.47 1 C3 0.1 75 - 11 - 58 COUT1 600 1 59 LV5 75 0.47 60 V5 600 1 61 RV5 600 1 62 LTV 75 0.47 63 TV 600 1 64 RTV 75 600 A f=100Hz, 0.3Vp-p signal is applied to Vcc and the output signals from Pins 38, 40, 52 and 54 are measured. CXA2079Q Fig. 3. Audio system (ripple rejection ratio) measurement circuit DC OUT AGND LOUT1 AGND2 COUT2 52 NC NC 10 100Hz, 0.3Vp-p 0.47 10k 10 10k 10 Measurement point 75 75 -com 36 34 33 35 10 0.47 0.47 22 42 41 40 39 38 37 48 47 44 46 45 43 50 49 0.1 10 10 10 1k 10k 10 10k 10 75 75 10k 10k 10k 0.1 51 VCC CIN1 BIAS YIN1 YIN2 CIN2 SDA SCL ADR NC 31 NC 30 NC 29 S-4 28 S2-4 27 0.1 C4 26 5.7k 1 600 RV4 25 75 Y4 24 0.47 5.7k 1 600 LV4 23 75 V4 22 0.47 S-3 21 S2-3 20 75 32 19 10k MUTE ROUT2 AGND2 COUT2 10k 10 53 VOUT1 10k 10 54 ROUT1 55 TRAP1 10k 10 56 YOUT1 57 VGND 10k 10 58 COUT1 600 1 5.7k 59 LV5 LV1 RV1 S2-1 V2 Y2 C2 S-2 LV3 LV2 RV2 S2-2 V3 Y3 RV3 11 12 13 14 15 16 17 18 5.7k 0.47 5.7k 0.1 0.47 V1 Y1 C1 1 2 3 5.7k 5.7k 0.1 0.47 75 1 75 600 1 600 600 75 1 75 0.47 7 5.7k 0.47 4 8 5 6 9 S-1 10 5.7k 1 75 600 75 0.47 C3 0.1 1 75 600 1 75 600 - 12 - 75 0.47 60 V5 600 1 5.7k 61 RV5 600 1 5.7k 62 LTV 75 0.47 63 TV 600 1 5.7k 64 RTV 75 Measurement point CXA2079Q Fig. 4. Audio system (output DC offset voltage) measurement circuit DC OUT AGND LOUT1 VOUT2 YOUT2 LOUT2 52 NC NC 10 40dB Measurement point 75 75 10k -com 36 34 33 35 10k 1k 0.47 22 42 41 40 39 38 37 10 10 10 47 46 45 44 43 0.1 10k 10 10k 10 75 75 10k 0.1 10 51 0.47 4.5V 49 50 48 NC NC BIAS YIN1 YIN2 CIN1 CIN2 SDA SCL ADR NC 31 NC 30 NC 29 S-4 28 S2-4 27 0.1 C4 26 1 RV4 25 0.47 Y4 24 1 LV4 23 0.47 V4 22 S-3 21 S2-3 20 75 600 75 600 75 32 19 10k MUTE ROUT2 VOUT2 YOUT2 LOUT2 10k 10 53 VOUT1 10k 10 54 ROUT1 55 TRAP1 10k 10 56 YOUT1 57 VGND LV1 RV1 S2-1 V2 Y2 C2 S-2 LV3 RV3 RV2 10 11 12 13 V1 Y1 C1 S-1 LV2 S2-2 V3 Y3 1 3 0.47 1 75 600 75 75 0.1 0.47 1 600 4 7 8 2 5 6 9 14 0.47 1 75 600 75 0.1 15 0.47 75 1 600 16 17 0.47 1 75 600 18 0.47 1 C3 0.1 75 - 13 - Fig. 5. Audio system (residual noise) measurement circuit 10k 10 58 COUT1 600 1 59 LV5 75 0.47 60 V5 600 1 61 RV5 600 1 62 LTV 75 0.47 63 TV 600 1 64 RTV 75 600 DC OUT LOUT1 AGND2 COUT2 AGND 52 VCC 10 CXA2079Q CXA2079Q I2C BUS Control Signal 34 SDA tBUF 33 SCL tLOW tHD;STA P S tR tHD;DAT S P tHIGH tF tSU;DAT tSU;STA tSU;STO Fig. 6. I2C BUS Control Signal Timing Chart Description of Operation The CXA2079Q is a TV I2C bus-compatible AV switch IC. The video system and the stereo audio system both have 6 inputs and 2 outputs each. 4 of the 6 video system inputs support S2 and S protocols. The desired inputs can be independently assigned to each output (in the audio system, the left and right channels are processed as one unit) by I2C bus control. However, the same input is assigned to both the video and audio system output 2. I2C BUS Registers 1) I2C BUS The I2C bus (inter-IC bus) is an inter-IC bus system developed by Philips. Two lines (SDA - serial data, SCL - serial clock) provide control over start, stop, data transfer, synchronization, and collision avoidance. The IC outputs are either open collector or open drain, forming a bus line in the wired OR format. SDA A A MSB LSB MSB LSB SCL S 1 2 3 4 5 6 7 8 9 1 2 9 S: Start condition; SDA is set "Low" when SCL is "High" P: Stop condition; SDA is set "High" when SCL is "High" A: Acknowledge; signal sent from the slave P Data is transmitted by MSB-first. One data unit consists of 8 bits, to which the acknowledge signal, which indicates that the data has been accepted by the slave, is attached at the end. Normally, the slave1 IC receives data at the rising edge of SCL and the master2 IC changes data at the falling edge of SCL. 1 Slave: An IC that is placed under the control of the master. In a normal system, all devices excluding the central microcomputer are slaves. 2 Master: A central microcomputer or other controlling IC. - 14 - CXA2079Q 2) Control Registers The CXA2079Q control is exercised by writing 2-byte data into the two 8-bit control registers which control the output selector circuits for the 2 outputs. S Slave address A DATA1 A DATA2 AP S: Start condition A: Acknowledge P: Stop condition Control register structure (DATA1 and DATA2) * All registers are set to "0" during IC power on. * "" indicates undefined. b7 Slave add. DATA1 DATA2 1 A-GAIN b6 0 S/COMP1 S/COMP2 b5 0 b4 1 V-IN1 AV-IN2 b3 0 b2 0 b1 ADR A-IN1 DC OUT b0 R/W R/W (1): Read/write mode 0: Control data write 1: Status register read ADR (1): This bit sets the slave address set by the address pin. 0: 90H 1: 92H A-GAIN (1): LOUT1/ROUT1 output gain selector 0: 0dB output 1: -6dB output S/COMP1 and S/COMP2 (1 each): S terminal input/composite signal input selectors By setting these bits to "0", when composite signal input is selected, YOUT/COUT output the inputs from YIN/CIN during video 1/2 output. 0: Composite signal inputs (TV, V1 to V5 inputs) 1: S terminal inputs (Y1/C1 to Y4/C4 inputs) V-IN1 (3 each): This bit selects the input signals output to each video output. 0: Mute 1: Selects the TV input 2: Selects the V1 and Y1/C1 inputs 3: Selects the V2 and Y2/C2 inputs 4: Selects the V3 and Y3/C3 inputs 5: Selects the V4 and Y4/C4 inputs 6: Selects the V5 input 7: Mute - 15 - CXA2079Q A-IN1 (3 each): This bit selects the input signals output to each audio output. 0: Mute 1: Selects the LTV/RTV inputs 2: Selects the LV1/RV1 inputs 3: Selects the LV2/RV2 inputs 4: Selects the LV3/RV3 inputs 5: Selects the LV4/RV4 inputs 6: Selects the LV5/RV5 inputs 7: Mute AV-IN2 (3): This bit selects the input signals output to output 2 (VOUT2, YOUT2/COUT2, LOUT2/ROUT2). Note) Both the video output and the audio output are selected at the same time only for AV-IN2. 0: Mute 1: Selects the TV and LTV/RTV inputs 2: Selects the V1, Y1/C1 and LV1/RV1 inputs 3: Selects the V2, Y2/C2 and LV2/RV2 inputs 4: Selects the V3, Y3/C3 and LV3/RV3 inputs 5: Selects the V4, Y4/C4 and LV4/RV4 inputs 6: Selects the V5 and LV5/RV5 inputs 7: Mute DC OUT (2): This bit sets the DC voltage output from Pin 36 (DC OUT). 0: 4.5V 1: 0V 2: 1.9V 3: 4.5V 3) Status Registers * When reading two bytes S Slave address A DATA1 A DATA2 NA P * When reading one byte S Slave address A DATA1 NA P S: Start condition A: Acknowledge NA: No acknowledge P: Stop condition When communication is to be terminated in the status register reading mode, the no-acknowledge signal is needed to assure that the master does not issue the acknowledge signal to the slave. It is possible to read only DATA1 of the status register by sending the no-acknowledge signal after DATA1. - 16 - CXA2079Q Status register structure (DATA1 and DATA2) b7 Slave add. DATA1 DATA2 1 S1SEL S1SEL b6 0 S2SEL S2SEL b5 0 S3SEL S3SEL b4 1 S4SEL S4SEL b3 0 S-C1 S-C3 b2 0 b1 ADR S-C2 S-C4 b0 1 S1SEL to S4SEL (1 each): S-1 to S-4 pin status 0: S-1 to S-4 pins are not grounded. 1: S-1 to S-4 pins are grounded. S1SEL to S4SEL are actually determined by comparing the S-1 to S-4 pin DC voltages with 3.5V. S-1 to S-4 pin DC voltage 3.5V or more 3.5V or less S1SEL to S4SEL 0 1 S-C1, S-C2, S-C3, S-C4 (2 each): S2-1, S2-2, S2-3 and S2-4 pin status 0: 4:3 video signal 1: 4:3 letter-box signal 2: 16:9 video squeezed signal 3: No signal S-C1 to S-C4 are actually determined by comparing the S2-1 to S2-4 pin DC voltages with two threshold. However, when the S-1 to S-4 pins are open, the outputs are fixed to "3". S2-1 to S2-4 pin DC voltage 1.3V or less 1.3V or more to 2.5V or less 2.5V or more S-1 to S-4 OPEN S-C1 to S-C4 0 1 2 3 4) Power-on Reset The CXA2079Q has an internal power-on reset function that sets each control register to "0" during IC power ON. The power-on reset VTH has hysteresis. Power-on reset released Power-on reset VCC 4.5V 5.6V - 17 - Application Circuit -com VIDEO 2 output COMB FILTER 0.1 0.47 0.1 48 47 34 44 42 39 33 38 46 45 43 22 41 40 37 4.7k 36 35 220 220 COMB FILTER 75 0.1 10 1k 0.47 51 50 49 * Depending on the output bias of the comb filters, pay attention to the polarities of the capacitors since the bias at Pins 43, 45, 49 and 51 is approximately 3.1V and 4.5V, respectively. * Connect Pin 32 to Vcc when setting the slave address of the IC to 92H. * The audio output can be muted by setting Pin 48 to 3.5V or more. * The TRAP (Pin 55) are of 3.58MHz subcarrier. * Pay attention to the polarities of the capacitors since each output of video system and audio system has optional bias, respectively. 32 NC NC VCC BIAS YIN1 YIN2 MUTE ROUT2 VOUT2 YOUT2 LOUT2 AGND2 COUT2 AGND 53 VOUT1 NC 30 NC 29 S-4 28 1 S2-4 27 0.1 C4 26 1 RV4 25 0.47 Y4 24 1 LV4 23 0.47 V4 22 S-3 21 S2-3 20 75 DC OUT 52 ADR NC 31 LOUT1 VIDEO 1 output 54 ROUT1 10p 620 55 TRAP1 180 56 YOUT1 57 VGND V1 Y1 C1 S-1 LV2 RV2 S2-2 V3 Y3 LV1 RV1 S2-1 V2 Y2 C2 1 4 7 11 0.47 75 75 75 1 1 470k 1 470k 0.47 8 10 0.1 2 3 5 6 9 12 0.1 75 1 13 S-2 LV3 RV3 14 15 0.47 75 16 17 0.47 1 470k 75 18 19 0.1 1 470k 75 1 0.47 0.47 1 470k 75 1 470k 75 CXA2079Q VIDEO 1 input VIDEO 2 input VIDEO 3 input Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. C3 - 18 - 58 COUT1 1 59 LV5 CIN1 CIN2 SDA SCL VIDEO 5 input 0.47 VIDEO 4 input 60 V5 1 61 RV5 1 62 LTV 0.47 TV input 63 TV 1 64 RTV CXA2079Q Example of Representative Characteristics Video system frequency response characteristics 8 TV, V1 to V5 VOUT1, VOUT2 Y1 to Y4 YOUT1, YOUT2 C1 to C4 COUT1, COUT2 Audio system frequency response characteristics 2 L/RTV, L/R1 to L/R5 LOUT1 (0dB) L/RTV, L/R1 to L/R5 LOUT2 0 Video system input/output gain [dB] 6 4 Y1/C1 to Y4/C4 VOUT1, VOUT2 Audio system input/output gain [dB] -2 2 -4 L/RTV, L/R1 to L/R5 LOUT1 (-6dB) -6 0 -2 100k -8 1M 10M Frequency [Hz] 100M 1k 10k 100k 1M Frequency [Hz] Audio system distortion vs. Input amplitude 10 f = 1kHz 400Hz HPF, 80kHz LPF 1 Total harmonic distortion [%] 0.1 LOUT1 output (0dB gain) LOUT2 output 0.01 0.002 0 1 2 Input amplitude [Vrms] 3 4 - 19 - CXA2079Q Package Outline Unit: mm 64PIN QFP(PLASTIC) 23.9 0.4 + 0.4 20.0 - 0.1 51 33 + 0.1 0.15 - 0.05 0.15 52 32 17.9 0.4 + 0.4 14.0 - 0.1 64 20 + 0.2 0.1 - 0.05 1 1.0 + 0.15 0.4 - 0.1 + 0.35 2.75 - 0.15 0.12 M PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-64P-L01 QFP064-P-1420 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 1.5g - 20 - 0.8 0.2 19 16.3 |
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