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CXA2006Q
Digital CCD Camera Head Amplifier
Description The CXA2006Q is a bipolar IC developed as a head amplifier for digital CCD cameras. This IC provides the following functions: correlated double sampling, AGC for the CCD signal, GCA for the lowband chroma signal, AMP for high-band chroma and line signals, A/D sample and hold, blanking, A/D reference voltage, and an output driver. Features * High sensitivity made possible by a high-gain AGC amplifier * Blanking function provided for the purpose of calibrating the CCD output signal black level * Regulator output pin provided for A/D converter reference voltage * Built-in GCA and AMP for amplifying video signals (chroma and line signals) from external sources * Built-in sample-and-hold circuits (for camera signals and for video signals) required by external A/D converters Absolute Maximum Ratings * Supply voltage VCC * Operating temperature Topr * Storage temperature Tstg * Allowable power dissipation PD Operating Conditions Supply voltage Applications Digital CCD cameras Structure Bipolar silicon monolithic IC 32 pin QFP (Plastic)
14 -20 to +75 -65 to +150 640
V C C mW
VCC1, 2, 3
4.5 to 5
V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E94X41B8X-PS
CXA2006Q
Block Diagram and Pin Configuration
CCDLEVEL
AGCCONT
CLPDM
GND1
VCC1
SHD
SHP
24
23
22
21
20
19
18
17
N.C.
PIN
25 AGCCLP
16
AGCCLP
DIN
26
SH1
SH2 AGC SH3 LPF CAMSH BLK
15
CLPOB
VCC2
27 COSCLP1
14
XRS
N.C.
28
COSCLP2
REF BOTTOM
REF TOP
13
PBLK
LIN/CH
29 LIN/CH SW LIN CLP VI SW AMP CENTER BIAS VISH CH/CL DC CENTER BIAS GCA DRV C/V SW OFFSET SW
12
OFFSET
GND2
30
11
VRT
RFCONT
31
10
VRB
PBRFC
32 MODE SWITCHING LOUTCLP
9
VCC3
1
2
3
4
5
6
7
8
VSHP
CAM/VIDEO
-2-
LOUTCLP
DRVOUT
CH/CL
PB/REC
GND3
PS
CXA2006Q
Pin Description Pin No. 1 Symbol CAM /VIDEO
25A 25A 68k
(VCC1, 2, 3 = 4.75V) Pin voltage Equivalent circuit Description Camera and video signal selector. Chroma signal and composite video signal selector. High-band chroma signal and low-band chroma signal selector. Power save mode.
2
PB/REC
1
VTH = 1.35V 3 CH/CL
127 1.35V
2 3 4 10k 24k
27k
4
PS
16.25k
Sampling 5 VSHP VTH = 1.32V
5 127 1.32V
Sample-and-hold pulse input for video.
10k Sampling
2mA 400A
6.25k
6 23 30
GND3 GND23 GND2
GND
Ground.
100A
200A
66k
1.1k
7
LOUTCLP
Approx. 2V
7 4A 1.27V 24k 16k 127 100k
Capacitor connection for LOUTCLP which clamps the output minimum level in modes which pass the composite video signal. (Recommended value: 0.1F)
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CXA2006Q
Pin No.
Symbol
Pin voltage
Equivalent circuit
Description
100A
4mA 8 127 DRVOUT
8
* Camera mode (CAM) VRB - 200mV < black level < VRB + 300mV * Composite DRVOUT video mode (LIN) VRB + 100mV * Chroma mode (CH, CL) Center voltage = (VRT - VRB)/2
Driver output for A/D converter capable of DC coupling. Dynamic range = 2Vp-p
1.5mA 1.5mA
50
30k
SW1 SW2 Mode 0 0 0 1 0 1 CH, CL CAM LIN --
2.1V SW1 SW2 10p
1 1
OFFSET
0: Closed 1: Open
9 20 27
VCC3 VCC1 VCC2
VCC
Power supply.
2V regulator output.
13.75k
10
10
VRB
2.0V
2V 2k 10k 100A
Be sure to decouple this pin near the IC pins to prevent the oscillation and external noise when this pin is not used. (Recommended capacitor value: 4.7F)
4V regulator output.
3.75k 4V 3k 1.1k 11
11
VRT
4.0V
20k
100A
100A
100A
Be sure to decouple this pin near the IC pins to prevent the oscillation and external noise when this pin is not used. (Recommended capacitor value: 4.7F)
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CXA2006Q
Pin No.
Symbol
Pin voltage
Equivalent circuit
Description
66k
100A
100A 127
Controls the output offset during camera mode.
12
12
OFFSET
0 to 3V
24k
23k
1.1k
10k
When 0V: less than (VRB - 200mV) When 3.0V: greater than (VRB + 300mV)
25A
25A 68k
Camera signal preblanking pulse input. Active when Low only during camera mode. Calibrates the black level of the AGC output waveform. When PBLK is Low, the DRVOUT potential is forced to 2V.
VTH = 1.35V 13 PBLK
13 Active: Low 24k 10k
127 1.35V 27k
VTH = 2.16V 14 XRS
12.25k
200
2.16V
127 14 5p 100A 2.5mA 200 10k
Camera signal sample-and-hold pulse input.
10.25k
Sampling
VTH = 1.45V 15 CLPOB
15
1.1k
66k
1.45V 127 100A 29k
Active: Low
10k
Clamp pulse used to clamp the optical black portion of the camera signal after it passes through the AGC amplifier.
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CXA2006Q
Pin No.
Symbol
Pin voltage
Equivalent circuit
Description
1.1k
2k
16
16
AGCCLP
Approx. 3V
50A
127
AGC clamp capacitor. (Recommended value: 0.1F)
2k
20A
AGC gain control.
4k 20k 38k
18
AGCCONT
0 to 3.0V
18
127 10k 40A 40A 20A 20A 20A 20A
When 0V: 8dB (Minimum gain) When 3.0V: 38dB (Maximum gain)
200
19
DIN input CCD signal CCDLEVEL black level: approx. 2.7V
40A
19
Enables monitoring of the SHD output camera signal.
21
SHP VTH = 2.38V
2.38V
25k
200 127 21 22 10k 200
Preset level sampleand-hold pulse input.
25k
40A
670A
22
SHD
Sampling
Data level sampleand-hold pulse input.
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CXA2006Q
Pin No.
Symbol
Pin voltage
Equivalent circuit
Description
1.1k
1.1k
66k
VTH = 1.45V 24 CLPDM
24
127 1.45V 29k 85A 85A
Clamp pulse used to clamp the dummy pixel portion of the input CCD signal.
Active: Low
14k
2k
25 26
PIN DIN
Black level: approx. 2.7V
90A 127 25 26 0.9A 200 36k 2k
CCD signal input.
1k 127 29
10k
29
LIN/CH
Clamp potential during LIN mode: approx. 2.4V During CH mode: approx. 2.7V
2.1V
LIN mode
200A
100A
2A
10k 19k 2.7V 26k CH mode 100A
Common input for the composite video signal (LIN) and high-band chroma signal (CH).
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CXA2006Q
Pin No.
Symbol
Pin voltage
Equivalent circuit
Description
50A 50A 41k
Gain control for the low-band chroma signal (CL). When 0V: 3.5dB (Minimum gain) When 3.0V: 15.5dB (Maximum gain)
31
RFCONT
0 to 3.0V
127 31 10k 1k
42k 50A 50A 0.86V 9k
127 32 10k 100A 100A 7.3k
32
PBRFC
Approx. 2.94V
46k 18k 10k
Low-band chroma signal (CL) input.
41k
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CXA2006Q
Electrical Characteristics Item Camera mode Symbol IDC
(Ta = 25C, VCC1, 2 and 3 = 4.5V, VCC4 = OPEN) Conditions AGCCONT = 0V, open between VRT and VRB CAM/VIDEO = 3V, PB/REC = 0V, CH/CL = 0V, PS = 3V Open between VRT and VRB CAM/VIDEO = 0V, PB/REC = 0V, CH/CL = 0V, PS = 3V Open between VRT and VRB CAM/VIDEO = 0V, PB/REC = 3V, CH/CL = 3V, PS = 3V RFCONT = 0V, open between VRT and VRB CAM/VIDEO = 0V, PB/REC = 3V, CH/CL = 0V, PS = 3V PS = 0V DIN = 1s, 10mVp-p pulse AGCCONT = 3V DIN = 1s, 600mVp-p pulse AGCCONT = 0V A CON max. - A CON min. Min. 31 Typ. 46 Max. Unit 60
LINE mode IDL
Current consumption CH mode
19
27
36 mA
IDCH
17
26
35
CL mode PS mode Maximum gain Minimum gain
IPCL IDP A CONT max. A CONT min.
16 6 36 -- 28
24 10 38 8 30
33 13 40 10 32 dB
AGC
Range of AGC G gain variance
Dynamic range maximum Dynamic range minimum Offset high DRV Offset low VRT DC level REF VRB DC level VRT - VRB BLK Offset LIN mode gain CH mode gain CL mode maximum gain CL mode minimum gain
AGCmax. AGCCONT = 3V D CLPOUT output signal at saturation level AGCmin. AGCCONT = 0V D CLPOUT output signal at saturation level CAOF high CAOF low VRTO VRBO VR BLKOF LIN G CH G VCC1, 2, 3 = 4.75V, OFFSET = 3V camera mode VCC1, 2, 3 = 4.75V, OFFSET = 0V camera mode VCC1, 2, 3 = 4.75V with a 400 load VCC1, 2, 3 = 4.75V with a 400 load VCC1, 2, 3 = 4.75V with a 400 load BLKOF (PBLK = 3V) - BLKOF (PBLK = 0V) LIN/CH = 3MHz, 500mVp-p, sine wave + offset voltage LIN/CH = 3MHz, 500mVp-p, sine wave
1.9
2.1
2.5 V
1.9
2.1
2.5
560 -- 3.97 1.9 1.9 -5 8.5 8.1
660 -270 4 2 2 8.5 9.5 9.1
-- mV -200 4.03 2.1 2.1 15 10.5 10.1 dB mV V
AMP
RF RFCONT = 3V CONmax. 15kHz 80mVp-p sine wave RF RFCONT = 0V CONmin. 15kHz 400mVp-p sine wave -9-
16
20.5
--
GCA
--
0.4
2
CXA2006Q
Electrical Characteristics Measurement Circuit
GND GND GND GND GND GND
PL1
PL2
PL3
VCC1 4.75V
V12 0 to 3V
CCDLEVEL
AGCCONT
CLPDM
GND1
SHD
VCC1
SHP
24 C4 1F AC V5 VCC2 4.75V C3 1F
23
22
21
20
19
18
N.C.
17 C7 0.1 PL4
GND
25 AGCCLP 26 SH1 SH2 AGC LPF CAMSH BLK SH3 27 COSCLP1 REF BOTTOM REF TOP
16
GND
15
GND
14
GND
29 LIN/CH SW LIN CLP 30 CENTER BIAS AMP VI SW C/V SW OFFSET SW
12
GND
VISH CH/CL DC
GND
31 CENTER BIAS GCA DRV
GND
32 MODE SWITCHING LOUTCLP
9
C2 0.047F
1
2
3
4
5
6
7
8 R2 22
PB/ REC
LOUTCLP
L
SW1 HL V7 3V
SW2 HL V8 3V
SW3 HL V9 3V
SW4 H V10 PL7 3V C5 0.1
R1 20k V13 3V GND
DRVOUT
CAM/ VIDEO
CH/CL
GND3
PS
VSHP
C6 25p
GND
GND
GND
GND
GND
GND
GND
GND
SW1 SW2 SW3 SW5 SW4 L H H L H L L L L L L H H H H L H L L L H L - 10 - OFF OFF
MODE CAM
ON
H
LIN
CL CH POWER SAVE
GND
AC V4
PBRFC
VCC3
VCC3 4.75V
C8 4.7
GND
V2 0 to 3V
RFCONT
SW6
OFF ON
GND
C1 V1 0 to 4.75V 0.1F GND2
VRT 11 R3 400 VRB 10
C9 4.7
GND
AC V3
OFF ON
SW5 LIN/ CH
28
COSCLP2
13
OFFSET
V15 0 to 3V
GND
N.C.
PBLK
PL6
GND
VCC2
XRS
PL5
GND
DIN
CLPOB
GND
PIN
AGCCLP
CXA2006Q
Measurement Timing Chart
1H 2s 1.5V PL4 (CLPOB) 2s 1H GND
1.5V PL1 (CLPDM) GND
1.5V PL6 (PBLK) GND 1H
V5 (DIN)
Different for each test
Equivalent to CCD signal black level V3 (CH) V4 (PBRFC) V1 + V3 (LIN)
Different for each test
PL2 (SHD) PL3 (SHP) PL5 (XRS) PL7 (VSHP)
2.5V GND
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CXA2006Q
Application Circuit
GND
GND
GND
GND
GND
CLPDM
SHD
SHP VCC
V12 0 to 3V
CCDLEVEL
AGCCONT
CLPDM
GND1
SHD
VCC1
SHP
24 1F CCD
23
22
21
20
19
18
N.C.
17 C7 0.1
CLPOB
25 AGCCLP 26 SH1 SH2 AGC LPF CAMSH BLK SH3 27 COSCLP1 REF BOTTOM REF TOP
16
15
VCC
14
28 LIN/CH LIN/CH 0.1F 29
COSCLP2
13
12 LIN/CH SW LIN CLP VI SW AMP CENTER BIAS C/V SW OFFSET SW 11 CH/CL DC CENTER BIAS GCA DRV 9 MODE SWITCHING LOUTCLP
GND
30
VISH
GND
31
10
4.7F VCC3 VCC
PBRFC
PBRFC 0.047F
32
1
2
3
4
5
6
7
8
CAM/ VIDEO
VSHP
PB/ REC
PS
LOUTCLP
CH/CL
DRVOUT
GND3
VRB A/D A/D IN
22
0.1 VSHP 3V 3V 3V 3V
GND
GND
GND
GND
GND
GND
GND
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
- 12 -
GND
0 to 3V
RFCONT
VRB
VRT
GND
GND2
VRT
GND
4.7F
OFFSET
0 to 3V
GND
N.C.
PBLK
PBLK
GND
VCC2
XRS
XRS
GND
1F
DIN
CLPOB
GND
PIN
AGCCLP
CXA2006Q
Description of Operation 1. Camera signal processing system Process the video signal processing pins as follows only in camera mode. <5> VSHP ... Connect to GND. <7> LOUTCLP ... Connect to GND. <29> LIN/CH ... Connect to GND. <31> RFCONT ... Connect to GND. <32> PBRFC ... Connect to GND via the capacitor (approx. 0.01F). Operating conditions The camera signal processing system operates when PS is high, CAM/VIDEO is low, PB/REC is low and CH/CL is high, or when PS is high, CAM/VIDEO is high, PB/REC is low and CH/CL is low. Camera signal processing system timing chart (when VCC = 4.75V)
Sig interval Precharge level CCD output OPB interval Idle transfer interval Sig interval
Signal level SHP SHD SH1 output SH2 output SH3 output CLPDM (2 dummy bit portion during the idle transfer interval) AGC output SH3 output -SH2 output XRS CLPOB (2 during the OPB interval) CAMSH output 2.16V PBLK (10 during the idle transfer interval) Basic black level 2.16V [3] 2.7V [1] [2] 2.7V
2s Black level
-N times
2s
10s
BLK output CAMVISW output 2.16V [4]
DRVOUT output [5]
Approx. 2.65V when OFFSET = 3V Approx. 1.73V when OFFSET = 0V
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CXA2006Q
CDS: The CCD signal from the CCD image sensor is input to PIN and DIN where correlated double sampling (CDS) is performed by SH1, SH2 and SH3. The precharge level of the CCD output signal is sampled, held and output by the SH2 output, and the signal level is sampled, held and output by the SH3 output. CDSCLP: The CDSCLP stabilizes the input signal DC level, clamps (CLPDM) the input signal during the idle transfer interval for the purpose of eliminating the AGC input offset, and synchronizes the DC level ([1], [2]) of SH2 and SH3. AGC: The gain can be varied from 8 to 38dB by adjusting the AGCCONT voltage control VAGCCONT from 0 to 3V. LPF: A primary low-pass filter is installed for the purpose of eliminating unused bands and white noise and improving S/N. CAMSH: The CAMSH is used for camera signal processing system. It is a sample-and-hold circuit which synchronizes the data read-in timing for the external A/D. AGCCLP: The basic black level is set ([3]) by clamping the AGC output waveform with the CLPOB clock during the OPB interval. The AGCCLP capacitance is connected to the AGCCLP pin. BLK: The black level is calibrated by blanking the black level signal of the AGC output waveform so that it does not fall below the basic black level and replacing the DC potential. ([4]) The signal is blanked when PBLK is low. C/VSW: When the CAM/VIDEO, PB/REC, CH/CL and PS pin voltages are set so that the camera signal processing system operates, C/VSW conducts the BLK output (camera signal) into the DRV. In addition, when these voltages are set so that the video signal processing system operates, C/VSW conducts the VISH output (video signal) into the DRV. OFFSET SW: The OFFSET SW selects [OFFSET], [CH/CLDC] or [LOUTCLP] as the offset adjustment input pin of the DRV block and activates these pins by selecting the CAM/VIDEO, PB/REC, CH/CL and PS pin voltages. When the camera signal processing system is in camera mode, the OFFSET pin is conducted [OFFSET], allowing the camera signal offset to be adjusted. ([5]) When the video signal processing system is in LIN mode, the LOUTCLP pin is conducted [LOUTCLP], clamping the video composite signal at its sync level and offsetting the signal. In addition, CH/CL mode conducts the CH/CL DC [CH/CLDC], which gives center potential to the high-band chroma and low-band chroma signals of the video signal. DRV: DRV drives the external A/D. Camera and video (LIN, CH, CL modes) signals are input by switching C/VSW, and offset adjusted signals are output from DRVOUT pin. - 14 -
CXA2006Q
REFBOTTOM, REFTOP: REFBOTTOM and REFTOP are reference voltage source for the external A/D. They are connected to VRT and VRB of the A/D, and 2V and 4V are supplied. MODE SWITCHING: MODE SWITCHING is a mode selection block which selects camera signal system or video signal system operation by selecting high or low potentials for the CAM/VIDEO, PB/REC, CH/CL and PS pins. PS is the power save pin, and power save functions when this pin is low.
2. Video signal processing system Operating conditions The video signal processing system has three modes: LIN signal mode, CH signal mode and CL signal mode. The video signal processing system operates in LIN signal mode when PS is high, CAM/VIDEO is high, PB/REC is low and CH/CL is high, or when PS is high, CAM/VIDEO is low, PB/REC is low and CH/CL is low. The video signal processing system operates in CH signal mode when PS is high, CAM/VIDEO is low, PB/REC is high and CH/CL is high. The video signal processing system operates in CL signal mode when PS is high, CAM/VIDEO is low, PB/REC is high and CH/CL is low, or when PS is high, CAM/VIDEO is low, PB/REC is high and CH/CL is high.
Video signal processing system timing chart LIN mode
LIN/CH input 2.4V
AMP output 9.5dB
2.1V VISP
DRVOUT output
2.1V
- 15 -
CXA2006Q
LIN signal mode LINCLP: The video composite signal is input to LIN/CH pin. LINCLP expands the input dynamic range, and sync tip clamps the input signal at 2.4V to allow full input. The input level and frequency are respectively 571mVp-p (Max.) and DC is up to 7MHz. LINAMP: This is a fixed gain amplifier with a gain of 9.5dB. LIN/CHSW: LIN/CHSW switches between the LIN signal and CH (high-band chroma) signal. The signals are switched according to the mode selection. VISH: The VISH is used for video signal processing system. It is a sample-and-hold circuit which synchronizes the data read-in timing for the external A/D. VISW: VISW switches between the LIN, CH and CL low-band chroma signals for the video signal processing system. The signals are switched according to the mode selection. LOUTCLP: LOUTCLP is a clamp circuit which operates when the LIN signal is output to the DRV. The clamp potential is the sync portion, and is 2.1V.
- 16 -
CXA2006Q
CH (high-band chroma) signal mode CENTER BIAS: The video high-band chroma signal is input to LIN/CH pin. CENTER BIAS expands the input dynamic range and sets a center DC bias so that the center potential of the SIN signal is 2.7V to allow full input. The input level and frequency are respectively 470mVp-p (Max.) and from 1 to 7MHz. CH/CL DC: CH/CL DC is a DC bias circuit which operates when the CH signal is output to the DRV. The DC bias potential is 3V. CH mode
LIN/CH input
2.7V
AMPOUT output 9.1dB
3V
VISH
DRVOUT output
3V
- 17 -
CXA2006Q
CL (low-band chroma) signal mode CENTER BIAS: The video low-band chroma signal is input to PBRFC pin. CENTER BIAS expands the input dynamic range and sets a center DC bias so that the center potential of the SIN signal is 2.94V to allow full input. The input level and frequency are respectively 1490mVp-p (Max.) and DC is up to 1.5MHz. GCA: The GCA amplifier controls the gain of the CL signal input to PBRFC. The gain can be varied from 0.4 to 20.5dB by adjusting the RFCONT voltage from 0 to 3V. CH/CL DC: CH/CL DC is a DC bias circuit which operates when the CL signal is output to the DRV. The DC bias potential is 3V. CL mode
PBREC input
2.94V
GCAOUT output 0.4 to 20.5dB
3V
VISH
DRVOUT output
3V
- 18 -
CXA2006Q
Example of Representative Characteristics
CAM mode AGCCONT control supply voltage characteristics
VAGCCONT vs. Gain 40
30
VCC = 4.5V
Gain [dB]
20
VCC = 5.0V
10
0 0.0
1.0
2.0
3.0
VAGCCONT [V]
CAM mode OFFSET control supply voltage characteristics
VOFFSET vs. OFFSET 700 600 500 400 VCC = 4.5V VCC = 4.75V VCC = 5.0V
OFFSET [mV]
300 200 100 0 -100 -200 -300 0.0 1.0 VOFFSET [V] 2.0 3.0
CL mode RFGCA gain control supply voltage characteristics
VRFCONT vs. Gain 26
20
Gain [dB]
VCC = 4.5V 10
VCC = 5.0V
0 0.0
1.0 VRFCONT [V]
2.0
3.0
- 19 -
CXA2006Q
CAM mode AGCCONT control temperature characteristics (VCC = 4.75V)
AGCCONT vs. Gain 40 -20C 27C 75C
30
Gain [dB]
20
10 VCC = 4.75V 0 0.0
1.0
2.0
3.0
AGCCONT [V]
CAM mode OFFSET control temperature characteristics
VOFFSET vs. OFFSET 700 600 500 400 75C 27C -20C
OFFSET [mV]
300 200 100 0 -100 VCC = 4.75V -200 -300 0.0 1.0 VOFFSET [V] 2.0 3.0
CL mode RFGCA gain control temperature characteristics
VRFCONT vs. Gain 22 20 -20C 27C 75C
Gain [dB]
10
VCC = 4.75V 0 -1 0.0
1.0 VRFCONT [V]
2.0
3.0
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CXA2006Q
CAM mode maximum signal amplitude temperature characteristics
Ta vs. VOUT (camera mode)
CH mode AMP gain temperature characteristics
Ta vs. Gain (CH mode) 11
2.50 2.40 minGain (in = 0.4Vp-p) 2.30 2.20 10
VOUT [Vp-p]
2.10 2.00 1.90
Gain [dB]
9 1.80 1.70 1.60 1.50 -20 0 20 Ta [C] 40 VCC = 4.75V 8 -20 VCC = 4.75V 0 20 Ta [C] 40 60
60
CL mode maximum signal amplitude temperature characteristics
Ta vs. VOUT (CL mode)
LIN mode AMP gain temperature characteristics
Ta vs. Gain (CL mode) 11
3.50 3.40 3.30 3.20 10 maxGain
VOUT [Vp-p]
3.10 3.00 2.90 2.80 2.70
Gain [dB]
9 VCC = 4.75V
2.60 2.50 -20 0 20 Ta [C] 40 60 8 -20 0 20 Ta [C] 40
VCC = 4.75V
60
- 21 -
CXA2006Q
VRT, VRB and output DC (CAM, LIN, CH and CL modes) temperature characteristics
Ta vs. VRT, VRB, DCOUT -30 4.00 -35 VRT
CH mode 2nd/3rd harmonic distortion temperature characteristics
Ta vs. 2nd /3rd harmonic distortion
2nd/3rd Harmonic Distortion [dB]
3.80
-40 -45
2nd: OUT = 1.8Vp-p
VRT, VRB, DCOUT [V]
3.60 3.40 3.20 3.00 2.80 2.60 2.40 2.20 2.00 1.80 -20 0 20 Ta [C] VRB 40 60 LinOutDC CHOutDC VCC = 4.75V CamOutDC (cont = 1.0V) CLOutDC
2nd: OUT = 1.4Vp-p -50 -55 -60 -65 -70 -75 -80 -20 0 20 Ta [C] 40 f = 5MHz VCC = 4.5V 60 3rd: OUT = 1.8Vp-p 3rd: OUT = 1.4Vp-p
CL mode 2nd/3rd harmonic distortion temperature characteristics
Ta vs. 2nd/3rd harmonic distortion -30 -35 -30 -35 2nd: IN = 800mVp-p, OUT = 1.8Vp-p 2nd: IN = 100mVp-p, OUT = 0.6Vp-p
LIN mode 2nd/3rd harmonic distortion temperature characteristics
Ta vs. 2nd/3rd harmonic distortion
2nd/3rd Harmonic Distortion [dB]
-40 -45 -50 -55 -60 -65 -70 -75 -80 -20
2nd/3rd Harmonic Distortion [dB]
3rd: OUT = 1.8Vp-p 2nd: OUT = 1.8Vp-p
-40 -45 -50 -55 -60 -65 -70 -75 -80 -20 0
2nd: OUT = 1.4Vp-p 3rd: OUT = 1.4Vp-p
3rd: IN = 800mVp-p, OUT = 1.8Vp-p f = 700kHz VCC = 4.5V 40 Ta [C] 60
3rd: IN = 100mVp-p, OUT = 0.6Vp-p 0 20
f = 5MHz VCC = 4.5V 20 Ta [C] 40 60
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CXA2006Q
Package Outline
Unit: mm
32PIN QFP (PLASTIC)
9.0 0.2 + 0.3 7.0 - 0.1 24 17 + 0.35 1.5 - 0.15
0.1
25
16
32
9
+ 0.2 0.1 - 0.1
1 0.8 + 0.15 0.3 - 0.1
8 + 0.1 0.127 - 0.05 0 to 10
0.24
M
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-32P-L01 QFP032-P-0707 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS
EPOXY RESIN SOLDER PLATING 42 ALLOY 0.2g
- 23 -
0.50
(8.0)

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