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Integrated Circuit Systems, Inc.
AV9107C-13
CPU Frequency Generator
The AV9107C-13 offers a tiny footprint solution for generating two simultaneous clocks. The AV9107C-13 uses a 20 MHz crystal to generate two PLL synthesis outputs of 20 and 40 MHz. The Output enable pin will tristate the 40 MHz output when low (maintaining the 20 MHz output runing in both logic levels). The power pin takes the device to a low current condition, shutting off the PLL and forcing both outputs low, when the PD# pin is low. There is a built-in pull-up on both the OE and PD# inputs. The device has advanced features which include on-chip loop filters, tristate outputs, and power-down capability. A minimum of external components - two decoupling capacitors and an optional ferrite bead - are all that are required for jitterfree operation.
General Description

Features
Patented on-chip Phase-Locked Loop with VCO for clock generation Provides two synthesized clocks Generates 20 and 40 MHz output frequencies. On-chip loop filter Low power CMOS technology Single +3.3 or +5 volt power supply 8-pin SOIC package
Pin Configuration
Block Diagram
Note: Crystal is 20 MHz
AV 9107-13 RevB052197
AV9107C-13
Functionality
OE 0 1
(at 14.318) MHz reference frequency input)
CLK1 20 MHz 20 MHz CLK2 Tristate 40 MHz
Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 8 PIN NAME OE GND X1/CLK0 X2 PD# CLK1 VDD CLK2 TYPE Input PWR Input Input PWR Output DESCRIPTION Output Enable - Tristates the 40 MHz output when low. Pull-Up Ground. Crystal Input or Input Clock frequency. Typically 20MHz crystal. Power Down. Shuts off chip when low outputs are driven low. Internall pull-up. Digital power supply (+5V DC). Clock2 output, divided by 2 from clock1 output, for 20MHz with 20MHz crystal. Output is synthesized.
Output Crystal Output (No Connect when clock used.). Output Clock 1 output 40MHz with 20MHz crystal.
Frequency Accuracy and Calculation
The accuracy of the frequencies produced by the AV9107C depends on the input frequency and the desired actual output frequency. The formula for calculating the exact output frequency is as follows: Output Frequency = Input Frequency X Where A = 2, 3, 4 ... 128, and B = 2, 3, 4 ...32. For example, to calculate the actual output frequency for a video monitor expecting a 44.900 MHz clock and using a 14.318 MHz input clock, the closest A/B ratio is 69/22, which gives an output of 44.906 MHz (within 0.02% of the target frequency). Generally, the AV9107 can produce frequencies within 0.1% of the desired output. A B
Allowable Input and Output Frequencies
The input frequency should be between 12 and 40 MHz and the A/B ratio should not exceed 24. The output should fall in the range of 12 to 80 MHz for CLK1 dnd CLK2. (See specification for 3.3V and 5V condition details).
Output Enable
The Output Enable feature tristates the CLK1 output clock pin. This places the selected output pins in a high inpedance state to allow for system level diagnostic testing. The divideby-2 output of CLK2 remains active on the AV9107C-13 for any OE state.
Power Down
The power down pin shuts off the entire chip to save current. A few milliseconds are required to reach full functioning speed from a power down state.
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AV9107C-13
Absolute Maximum Ratings
AVDD, VDD referenced to GND . . . . . . . . . . . . . . . 7V Operating temperature under bias. . . . . . . . . . . . . . . . 0C to +70C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Voltage on I/O pins referenced to GND. . . . . . . . . . . GND -0.5V to VDD +0.5V Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 Watts Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics at 5.0V
PARAMETER Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage Output High Voltage, Note 1 Output Low Current, Note 1 Output High Current, Note 1 Supply Current Output Frequency Change over Supply and Temperature Stand by Supply Current Pull-up Resistor, Note 1 Output Rise Time 0.8 to 2.0V, Note 1 Output Fall Time 2.0 to 0.8V, Note 1 Rise Time 20% to 80% VDD, Note 1 Fall Time 80% to 20% VDD, Note 1 Duty Cycle, Note 1 Jitter, One Sigma, Note 1 Jitter, Absolute, Notes 1, 3 Input Frequency, Note 1 Output Frequency, Note 1 Power-up Time, Note 1 SYMBOL VIL VIH IIL IIH VOL VOH IOL IOH IDD Fd IDDSTDBY Rpu VIN=0V VIN=VDD
Operating VDD = +4.5V to +5.5V; TA =0C to 70C unless otherwise stated
DC Characteristics TEST CONDITIONS MIN 2.0 2.0 2.4 22.0 AC Characteristics Tr Tf Tr Tf Dt Tjis Tjab Fi Fo Tpu Clock1 15pF load 15pF load 15pF load 15pF load 15pF load 10,000 samples 10,000 samples 45.0 -500.0 14 28 0.65 0.55 1.5 1.1 40.0 200 20 40 130 1.60 1.2 3.5 2.2 55.0 120.0 500.0 40 80 300 ns ns ns ns % ps ps MHz MHz s TYP 6.0 0.25 3.25 35.0 -50.0 18.0 0.002 12.0 380.0 MAX 0.8 16.0 2.0 0.40 -35.0 40.0 0.05 50.0 800.0 UNITS V V A A V V mA mA mA % A k ohms
IOL=10mA IOH=-30mA VOL=0.8V VOH=2.0V No load With respect to typical frequency Note 1 Note 2 VIN = VDD -1V
Note 1: Note2: Note3:
Parameter is guaranteed by design and characterization. Not 100% tested in production. AV9107C-13 with the power down pin low (active). Absolute jitter measured as the shortest and longest period difference to the mean period of the sample set. 3
AV9107C-13
Electrical Characteristics at 3.3V
Operating VDD = +3.0V to +3.7V; TA =0C to 70C unless otherwise stated
DC Characteristics PARAMETER Input Low Voltage Input High Voltage Input Low Current, Note1 Input High Current, Note 1 Output Low Voltage, Note 1 Output High Voltage, Note 1 Output Low Current, Note 1 Output High Current, Note 1 Supply Current, Note 1 Standby Supply Current, Notes 1, 2 Output Frequency Change over Supply and Temperature, Note1 Pull-up Resistor, Note 1 Rise Time 20% to 80% VDD, Note 1 Fall Time 80% to 20% VDD, Note 1 Duty Cycle, Note 1 Jitter, One Sigma, Note 1 Jitter, Absolute, Notes 1, 3 Input Frequency, Note 1 Output Frequency, Note 1 Power-up Time, Note 1 SYMBOL VIL VIH IIL IIH VOL VOH IOL IOH IDD IDDSTDBY Fd Rpu With respect to typical frequency VIN = VDD - 0.5V AC Characteristics Tr Tf Dt Tjis Tjab Fi Fo Tpu Clock1 15pF load 15pF load 15pF load @ 50% 10,000 samples 10,000 samples 42 500.0 12 24 2.0 1.2 40.0 200 20 40 265 3.4 2.2 52 120.0 500.0 25 50 500 ns ns % ps ps MHz MHz s VIN=0V VIN=VDD IOL=6mA IOH=-5mA VOL=0.2VDD VOL=0.7VDD Unloaded TEST CONDITIONS MIN 0.7VDD -2.0 0.85xVDD 15.0 TYP 2.5 0.15 0.92xVDD 22.0 -17.0 11.0 13.0 0.002 0.55 MAX 0.20VDD 7.0 2.0 0.1xVDD -10.0 25.0 40.0 0.01 1.0 UNITS V V A A V V mA mA mA A % M ohms
Note 1: Note2: Note3:
Parameter is guaranteed by design and characterization. Not 100% tested in production. AV9107C-13 with the power down pin low (active). Absolute jitter measured as the shortest and longest period difference to the mean period of the sample set.
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AV9107C-13
8-Pin Plastic SOIC Package
Ordering Information
Example:
AV9107C-13CS08
XXX XXXX-PPP M X#W
Lead Count & Package Width Package Type
S=SOIC Lead Count=1, 2 or 3 digits W=.3 SOIC or .6 DIP; None=Standard Width
Pattern Number (2 or 3 digit number for parts with ROM code patterns, if applicable) Device Type (consists of 3 or 4 digit numbers) Prefix
ICS, AV=Standard Device; GSP=Genlock Device
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