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Features
* Incorporates the ARM7TDMI TM ARM Thumb processor
- High-performance 32-bit RISC architecture - High-density 16-bit instruction set - Leader in MIPS/Watt - Embedded ICE In Circuit Emulation 4K bytes internal RAM Fully programmable External Bus Interface (EBI) - Maximum external address space of 64M bytes - Up to eight chip selects - Software programmable 8/16-bit external databus Eight-level priority, individually maskable, vectored interrupt controller - Four External interrupts, including a high priority low latency interrupt request 32 Programmable I/O lines Three-channel 16-bit timer/counter - Three external clock inputs - Two multi-purpose I/O pins per channel Two USARTs - Two dedicated Peripheral Data Controller (PDC) channels per USART Programmable watchdog timer Low-power idle and power-down modes Fully static operation: 0 Hz to 33 MHz 2.7V to 3.6V operating range Available in a 100-lead TQFP package
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16/32-Bit Microcontroller AT91M40400 Summary
Full datasheet (lit# 0768B) also available by e-mailing literature@atmel.com
Description
The AT91M40400 is a member of the Atmel AT91 16/32-bit Microcontroller family which is based on the ARM7TDMI embedded processor. This processor has a highperformance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. The AT91 ARM-based MCU family also features Atmel's high-density, nonvolatile memory technology. The on-chip Flash program memory is in-system programmable. The AT91M40400 has a direct connection to off-chip memory, including Flash, through the External Bus Interface. The device is manufactured using Atmel's high-density CMOS technology. By combining the ARM7TDMI microcontroller core with an on-chip RAM and a wide range of peripheral functions on a monolithic chip, the Atmel AT91M40400 is a powerful microcontroller that provides a flexible, cost-effective solution to many compute-intensive embedded control applications.
Rev. 0768BS-08/98
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Pin Configuration
Figure 1. AT91M40400 Pinout (Top View)
NWR0/NWE NWR1/NUB 77 P25/MCKO P27/NCS3 P26/NCS2 P22/RXD1 76 NRD/NOE NWDOVF P24/BMS
NWAIT
NRST 79
NCS1
NCS0
MCKI
GND
GND
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
78
GND
VDD
VDD
TMS
VDD
TDO
TCK
P23
TDI
A0/NLB GND A1 A2 A3 A4 A5 A6 A7 VDD A8 A9 A10 A11 A12 A13 A14 GND GND A15 A16 A17 A18 A19 P28/A20/CS7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
75 74 73 72 71 70 69 68 67 66 65
P21/TXD1/NTRI P20/SCK1 P19 P18 P17 P16 P15/RXD0 P14/TXD0 P13/SCK0 P12/FIQ GND P11/IRQ2 P10/IRQ1 VDD VDD P9/IRQ0 P8/TIOB2 P7/TIOA2 P6/TCLK2 P5/TIOB1 P4/TIOA1 P3/TCLK1 GND GND P2/TIOB0
AT91M40400 100-Lead TQFP
64 63 62 61 60 59 58 57 56 55 54 53 52 51
P29/A21/CS6
P30/A22/CS5
2
AT91M40400
P31/A23/CS4
P0/TCLK0
P1/TIOA0
GND
D0
D1
D2
D3
D4
D5
D6
D7
D8
VDD
VDD
D9
VDD
D10
D11
D12
D13
D14
D15
AT91M40400
Table 1. AT91M40400 Pin Description
Module Name A0-A23 D0-D15 NCS0-NCS3 CS4-CS7 NWR0 NWR1 EBI NRD NWE NOE NUB NLB NWAIT BMS FIQ AIC IRQ0-IRQ2 TCLK0-TCLK2 Timer TIOA0-TIOA2 TIOB0-TIOB2 SCK0-SCK1 USART TXD0-TXD1 RXD0-RXD1 PIO WD Clock MCKO NRST Reset NTRI TMS TDI ICE TDO TCK VDD Power GND Ground Test Data Output Test Clock Power Output Input --Schmidt trigger, internal pull-up Tristate Mode Select Test Mode Select Test Data Input Input Input Input low --Sampled during reset Schmidt trigger, internal pull-up Schmidt trigger, internal pull-up Master Clock Output Hardware Reset Input Output Input -low Schmidt trigger, internal pull-up P0-P31 NWDOVF MCKI External Interrupt Request Timer External Clock Multipurpose Timer I/O pin A Multipurpose Timer I/O pin B External Serial Clock Transmit Data Output Receive Data Input Parallel IO line Watchdog overflow Master Clock Input Input Input I/O I/O I/O Output Input I/O Output Input --------low -Open drain Schmidt trigger PIO controlled after reset PIO controlled after reset PIO controlled after reset PIO controlled after reset PIO controlled after reset PIO controlled after reset PIO controlled after reset Function Address Bus Data Bus Chip Select Chip Select Lower Byte 0 Write Signal Upper Byte 1 Write Signal Read Signal Write Enable Output Enable Upper Byte Select Lower Byte Select Wait Input Boot Mode Select Fast Interrupt Request Type Output I/O Output Output Output Output Output Output Output Output Output Input Input Input Active Level --low high low low low low low low low low --Sampled during reset PIO controlled after reset A23-A20 after reset Used in Byte Write Option Used in Byte Write Option Used in Byte Write Option Used in Byte Select Option Used in Byte Select Option Used in Byte Select Option Used in Byte Select Option Comments All valid after reset
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Block Diagram
Figure 2. AT91M40400 Block Diagram
TMS TDO TDI TCK Reset NRST
Embedded ICE
D0-D15
ARM7TDMI Core
ASB
MCKI Clock P25/MCKO
RAM 4K bytes
EBI: External Bus Interface
A1-A19 A0/NLB NRD/NOE NWR0/NWE NWR1/NUB NWAIT NCS0 NCS1 P26/NCS2 P27/NCS3 P28/A20/CS7 P29/A21/CS6 P30/A22/CS5 P31/A23/CS4 P I O
ASB Controller P I O AIC: Advanced Interrupt Controller
AMBA Bridge EBI User Interface
P12/FIQ P9/IRQ0 P10/IRQ1 P11/IRQ2
P13/SCK0 P14/TXD0 P15/RXD0 P20/SCK1 P21/TXD1/NTRI P22/RXD1
USART0
2 PDC Channels APB 2 PDC Channels
TC: Timer Counter TC0
P0/TCLK0 P3/TCLK1 P6/TCLK2 P1/TIOA0 P2/TIOB0 P4/TIOA1 P5/TIOB1 P7/TIOA2 P8/TIOB2
USART1
TC1 TC2
PS: Power Saving P16 P17 P18 P19 P23 P24/BMS WD: Watchdog Timer NWDOVF
Chip ID
PIO: Parallel I/O Controller
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AT91M40400
AT91M40400
Architectural Overview
The AT91M40400 architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It interfaces the processor with the on-chip 32-bit memories and the external memories and devices by means of the External Bus Interface (EBI). The APB is designed for accesses to on-chip peripherals and is optimized for low power consumption. The AMBA Bridge provides an interface between the ASB and the APB. An on-chip Peripheral Data Controller (PDC) transfers data between the on-chip USARTs and the on and off-chip memories without processor intervention. Most importantly, the PDC removes the processor interrupt handling overhead and significantly reduces the number of clock cycles required for a data transfer. It can transfer up to 64k contiguous bytes without reprogramming the starting address. As a result, the performance of the microcontroller is increased and the power consumption reduced. The AT91M40400 peripherals are designed to be programmed with a minimum number of instructions. Each peripheral has a 16K byte address space allocated in the upper 3M bytes of the 4G byte address space. Except for the interrupt controller, the peripheral base address is the lowest address of its memory space. The peripheral register set is composed of control, mode, data, status and interrupt registers. To maximize the efficiency of bit manipulation, frequently written registers are mapped into three memory locations. The first address is used to set the individual register bits, the second resets the bits and the third address reads the value stored in the register. A bit can be set or reset by writing a one to the corresponding position at the appropriate address. Writing a zero has no effect. Individual bits can thus be modified without having to use costly read-modifywrite and complex bit manipulation instructions. All of the external signals of the on-chip peripherals are under the control of the Parallel I/O controller. The PIO controller can be programmed to insert an input filter on each pin or generate an interrupt on a signal change. After reset, the user must carefully program the PIO Controller in order to define which peripheral signals are connected with off-chip logic. The ARM7TDMI processor operates in little-endian mode in the AT91M40400 microcontroller. The processor's internal architecture and the ARM and Thumb instruction sets are described in the ARM7TDMI Datasheet. The on-chip peripherals are described in the subsequent sections of this datasheet. Electrical characteristics are documented in a separate datasheet entitled "AT91M40400 Electrical and Mechanical Characteristics". The ARM Standard In-Circuit-Emulation debug interface is supported via the ICE port of the AT91M40400 microcontroller. (This is not a standard IEEE 1149.1 JTAG Boundary Scan interface)
PDC: Peripheral Data Controller
The AT91M40400 has a 4-channel PDC dedicated to the two on-chip USARTs. One PDC channel is connected to the receiving channel and one to the transmitting channel of each USART. The user interface of a PDC channel is integrated in the memory space of each USART channel. It contains a 32-bit address pointer register (US_RPR or US_TPR) and a 16bit byte count register (US_RCR or US_TCR). When the programmed number of bytes are transferred, an end of transfer interrupt is generated by the corresponding USART.
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EBI: External Bus Interface
The EBI generates the signals which control the access to the external memory or peripheral devices. The EBI is fully programmable and can address up to 64M bytes. It has eight chip selects and a 24-bit address bus, the upper four bits of which are multiplexed with a chip select. The 16-bit data bus can be configured to interface with 8or 16-bit external devices. Separate read and write control signals allow for direct memory and peripheral interfacing. The EBI supports different access protocols allowing single clock cycle memory accesses. The main features are: * External Memory Mapping * Up to 8 chip select lines * 8- or 16-bit data bus * Byte write or byte select lines * Remap of boot memory * Two different read protocols * Programmable wait state generation * External wait request * Programmable data float time
PIO: Parallel I/O Controller
The AT91M40400 has 32 programmable I/O lines. Six pins on the AT91M40400 are dedicated as general purpose I/O pins (P16, P17, P18, P19, P23 and P24). Other I/O lines are multiplexed with an external signal of a peripheral to optimize the use of available package pins. The PIO controller enables generation of an interrupt on input change and insertion of a simple input glitch filter on any of the PIO pins.
USART: Universal Synchronous/Asynchronous Receiver/Transmitter
The AT91 provides two identical, full-duplex, universal synchronous/asynchronous receiver/transmitters that interface to the APB and are connected to the Peripheral Data Controller. The main features are: * Programmable Baud Rate Generator * Parity, Framing and Overrun Error Detection * Line Break Generation and Detection * Automatic Echo, Local Loopback and Remote Loopback channel modes * Multi-drop Mode: Address Detection and Generation * Interrupt Generation * Two Dedicated Peripheral Data Controller channels * 5-, 6-, 7- and 8-bit character length
AIC: Advanced Interrupt Controller
The AT91 has an 8-level priority, individually maskable, vectored interrupt controller. This feature substantially reduces the software and real time overhead in handling internal and external interrupts. The interrupt controller is connected to the NFIQ (fast interrupt request) and the NIRQ (standard interrupt request) inputs of the ARM7TDMI processor. The processor's NFIQ line can only be asserted by the external fast interrupt request input: FIQ. The NIRQ line can be asserted by the interrupts generated by the on-chip peripherals and the external interrupt request lines: IRQ0 to IRQ2. An 8-level priority encoder allows the customer to define the priority between the different NIRQ interrupt sources. Internal sources are programmed to be level sensitive or edge triggered. External sources can be programmed to be positive or negative edge triggered or high or low level sensitive.
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AT91M40400
AT91M40400
TC: Timer Counter
The AT91M40400 features a Timer Counter block which includes three identical 16-bit timer counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. Each Timer Counter channel has 3 external clock inputs, 5 internal clock inputs, and 2 multi-purpose input/output signals which can be configured by the user. Each channel drives an internal interrupt signal which can be programmed to generate processor interrupts via the AIC (Advanced Interrupt Controller). The Timer Counter block has two global registers which act upon all three TC channels. The Block Control Register allows the three channels to be started simultaneously with the same instruction. The Block Mode Register defines the external clock inputs for each Timer Counter channel, allowing them to be chained.
WD: Watchdog Timer
The AT91 series microcontrollers have an internal watchdog timer which can be used to prevent system lock-up if the software becomes trapped in a deadlock.
PS: Power Saving
The AT91M40400 Power Saving module provides a lowpower Idle Mode. In Idle Mode, the CPU clock is deactivated while all on-chip peripherals and the RAM remain active. The contents of the on-chip RAM and all the special function registers remain unchanged during this mode. The Idle Mode can be terminated by any enabled interrupt or by a hardware Reset.
SF: Special Function
The AT91M40400 provides registers which implement the following special functions. * Chip identification * RESET status
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