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a
FEATURES All-In-One Synchronous Buck Driver Bootstrapped High-Side Drive One PWM Signal Generates Both Drives Anticross-Conduction Protection Circuitry Pulse-by-Pulse Disable Control APPLICATIONS Multiphase Desktop CPU Supplies Mobile Computing CPU Core Power Converters Single-Supply Synchronous Buck Converters Standard-to-Synchronous Converter Adaptations
Dual Bootstrapped MOSFET Driver with Output Disable ADP3413
FUNCTIONAL BLOCK DIAGRAM
VCC BST
IN OVERLAP PROTECTION CIRCUIT OD 3
DRVH
SW
DRVL
ADP3413
GENERAL DESCRIPTION
PGND
The ADP3413 is a dual MOSFET driver optimized for driving two N-channel MOSFETs which are the two switches in a nonisolated synchronous buck power converter. Each of the drivers is capable of driving a 3000 pF load with a 20 ns propagation delay and a 30 ns transition time. One of the drivers can be bootstrapped, and is designed to handle the high-voltage slew rate associated with "floating" high-side gate drivers. The ADP3413 includes overlapping drive protection (ODP) to prevent shoot-through current in the external MOSFETs. The OD pin provides high speed control to quickly turn off both gate drives. The ADP3413 is specified over the commercial temperature range of 0C to 70C and is available in an 8-lead SOIC package.
7V D1 VCC 12V
ADP3413
BST
CBST IN DRVH
Q1
SW
DELAY +1V DRVL 1V PGND OD 3 Q2
REV. 0
Figure 1. General Application Circuit
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2001
ADP3413-SPECIFICATIONS1(T = 0 C to 70 C, VCC = 7 V, BST = 4 V to 26 V, OD > 2 V, unless otherwise noted.)
A
Parameter SUPPLY Supply Voltage Range Quiescent Current OD INPUT Input Voltage High2 Input Voltage Low2 Propagation Delay Time PWM INPUT Input Voltage High2 Input Voltage Low2 HIGH-SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Transition Times3 (See Figure 2) Propagation Delay3, 4 (See Figure 2) LOW-SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Transition Times3 (See Figure 2) Propagation Delay3, 4 (See Figure 2)
Symbol VCC ICCQ
Conditions
Min 4.15
Typ
Max 7.5 2
Unit V mA V V ns ns V V ns ns ns ns ns ns ns ns
1 2.0
tpdlOD tpdhOD 2.3
15 15
0.8 30 30
0.8 VBST - VSW = 5 V VBST - VSW = 7 V VBST - VSW = 5 V VBST - VSW = 7 V VBST - VSW = 7 V, CLOAD = 3 nF VBST - VSW = 7 V, CLOAD = 3 nF VBST - VSW = 7 V VBST - VSW = 7 V VCC = 5 V VCC = 7 V VCC = 5 V VCC = 7 V VCC = 7 V, CLOAD = 3 nF VCC = 7 V, CLOAD = 3 nF VCC = 7 V VCC = 7 V 3.0 2.0 1.25 1.0 36 20 65 22 3.0 2.0 1.5 1.0 27 19 30 17 5.0 3.5 2.5 2.5 47 30 86 32 5.0 3.5 3.0 2.5 35 26 35 25
trDRVH tfDRVH tpdhDRVH tpdlDRVH
trDRVL tfDRVL tpdhDRVL tpdlDRVL
NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. 2 Logic inputs meet typical CMOS I/O conditions for source/sink current (~1 A). 3 AC specifications are guaranteed by characterization, but not production tested. 4 For propagation delays, "tpdh" refers to the specified signal going high; "tpdl" refers to it going low. Specifications subject to change without notice.
-2-
REV. 0
ADP3413
ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE
Model Temperature Package Range Description 8-Lead Standard Small Outline (SOIC) Package Option SO-8
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +8 V BST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +30 V BST to SW . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +8 V SW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5.0 V to +25 V OD, IN . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VCC + 0.3 V Operating Ambient Temperature Range . . . . . . . 0C to 70C Operating Junction Temperature Range . . . . . . 0C to 125C JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155C/W JC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40C/W Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300C
*This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged. Unless otherwise specified, all voltages are referenced to PGND.
ADP3413JR 0C to 70C
PIN CONFIGURATION
BST 1 IN 2 OD 3 VCC 4
8
DRVH SW PGND DRVL
ADP3413
TOP VIEW (Not To Scale)
7 6 5
PIN FUNCTION DESCRIPTIONS
Pin 1
Mnemonic BST
Function Floating Bootstrap Supply for the Upper MOSFET. A capacitor connected between BST and SW pins holds this bootstrapped voltage for the high-side MOSFET as it is switched. The capacitor should be chosen between 100 nF and 1 F. TTL-level Input Signal, which has primary control of the drive outputs. Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low. Input Supply. This pin should be bypassed to PGND with ~1 F ceramic capacitor. Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET. Power Ground. Should be closely connected to the source of the lower MOSFET. This pin is connected to the buck-switching node, close to the upper MOSFET's source. It is the floating return for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent turnon of the lower MOSFET until the voltage is below ~1 V. Thus, according to operating conditions, the high-low transition delay is determined at this pin. Buck Drive. Output drive for the upper (buck) MOSFET.
2 3 4 5 6 7
IN OD VCC DRVL PGND SW
8
DRVH
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3413 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
-3-
ADP3413
IN tpdlDRVL tfDRVL tpdlDRVH trDRVL
DRVL
tfDRVH tpdhDRVH trDRVH
DRVH-SW
VTH
VTH
tpdhDRVL SW 1V
Figure 2. Nonoverlap Timing Diagram (Timing Is Referenced to the 90% and 10% Points Unless Otherwise Noted)
OD
tpdlOD DRVH OR DRVL 90% tpdhOD
10%
Figure 3. Output Disable Timing Diagram
-4-
REV. 0
Typical Performance Characteristics- ADP3413
T DRVH 5V/DIV R3 TA = 25 C VCC = 5V
T TA = 25 C VCC = 5V R3 DRVL 2V/DIV
TIME - ns
50 CLOAD = 3nF
DRVH 5V/DIV
45
DRVH @ VCC = 5V
40
DRVH @ VCC = 7V DRVL @ VCC = 5V
IN R2 R1 2V/DIV 40ns/DIV DRVL 5V/DIV
35
R2 R1
IN 2V/DIV 40ns/DIV
30
25
DRVH @ VCC = 7V
20
0
25 100 50 75 JUNCTION TEMPERATURE - C
125
TPC 1. DRVH Fall and DRVL Rise Times
TPC 2. DRVL Fall and DRVH Rise Times
TPC 3. DRVH and DRVL Rise Times vs. Temperature
35 DRVL @ VCC = 7V 30 25 DRVL @ VCC = 5V
TIME - ns
55 DRVH @ VCC = 5V 50 DRVH @ VCC = 7V 45 40 35 30 25
TIME - ns
37
32 DRVL @ VCC = 7V
27
TIME - ns
20 15 10 5 0 DRVH @ VCC = 7V
22
17 DRVL @ VCC = 5V DRVL @ VCC = 7V 12 DRVL @ VCC = 5V
DRVH @ VCC = 5V
DRVH @ VCC = 5V DRVH @ VCC = 7V
20 15
0 25 50 75 100 JUNCTION TEMPERATURE - C 125
10 1.0
2.0 3.0 4.0 LOAD CAPACITANCE - nF
5.0
7 1.0
1.5
2.0 2.5 3.0 3.5 4.0 4.5 LOAD CAPACITANCE - nF
5.0
TPC 4. DRVH and DRVL Fall Times vs. Temperature
TPC 5. DRVH and DRVL Rise Times vs. Load Capacitance
TPC 6. DRVH and DRVL Fall Times vs. Load Capacitance
35 30 TA = 25 C CLOAD = 3nF
8.5 8
SUPPLY CURRENT - mA
25 VCC = 7V 20 15 10 5 0 VCC = 5V
SUPPLY CURRENT - mA
VCC = 7V 7.5 7 6.5 6 VCC = 5V 5.5 5 CLOAD = 3nF fIN = 250kHz
0
200
400 600 800 1000 1200 1400 IN FREQUENCY - kHz
0
100 25 50 75 JUNCTION TEMPERATURE - C
125
TPC 7. Supply Current vs. Frequency
TPC 8. Supply Current vs. Temperature
REV. 0
-5-
ADP3413
THEORY OF OPERATION
The ADP3413 is a dual MOSFET driver optimized for driving two N-channel MOSFETs in a synchronous buck converter topology. A single PWM input signal is all that is required to properly drive the high-side and the low-side FETs. Each driver is capable of driving a 3 nF load. A more detailed description of the ADP3413 and its features follows. Refer to the Functional Block Diagram.
Low-Side Driver
To prevent the overlap of the gate drives during Q2's turn OFF and Q1's turn ON, the overlap circuit provides a internal delay that is set to 50 ns. When the PWM input signal goes high, Q2 will begin to turn OFF (after a propagation delay), but before Q1 can turn ON the overlap protection circuit waits for the voltage at DRVL to drop to around 10% of VCC. Once the voltage at DRVL has reached the 10% point, the overlap protection circuit will wait for a 20 ns typical propagation delay. Once the delay period has expired, Q1 will begin turn ON.
Output Disable
The low-side driver is designed to drive low RDS(ON) N-channel MOSFETs. The maximum output resistance for the driver is 3.5 for sourcing and 2.5 for sinking gate current. The low output resistance allows the driver to have 30 ns rise and fall times into a 3 nF load. The bias to the low-side driver is internally connected to the VCC supply and PGND. When the driver is enabled, the driver's output is 180 degrees out of phase with the PWM input. When the ADP3413 is disabled, the low-side gate is held low.
High-Side Driver
The disable input is used to turn off the buck converter. If the circuits running off of the buck converter are not needed, the ADP3413 can be shutdown to conserve power. When the OD pin is low, the ADP3413 is disabled. The DRVH and DRVL outputs are forced low, turning the buck converter OFF.
APPLICATION INFORMATION Supply Capacitor Selection
The high-side driver is designed to drive a floating low RDS(ON) N-channel MOSFET. The maximum output resistance for the driver is 3.5 for sourcing and 2.5 for sinking gate current. The low output resistance allows the driver to have 30 ns rise and fall times into a 3 nF load. The bias voltage for the high-side driver is developed by an external bootstrap supply circuit, which is connected between the BST and SW pins. The bootstrap circuit comprises a diode, D1, and bootstrap capacitor, CBST. When the ADP3413 is starting up, the SW pin is at ground, so the bootstrap capacitor will charge up to VCC through D1. When the PWM input goes high, the high-side driver will begin to turn the high-side MOSFET, Q1, ON by pulling charge out of CBST. As Q1 turns ON, the SW pin will rise up to VIN, forcing the BST pin to VIN + VC(BST), which is enough gate to source voltage to hold Q1 ON. To complete the cycle, Q1 is switched OFF by pulling the gate down to the voltage at the SW pin. When the low-side MOSFET, Q2, turns ON, the SW pin is pulled to ground. This allows the bootstrap capacitor to charge up to VCC again. The high-side driver's output is in phase with the PWM input. When the driver is disabled, the high-side gate is held low.
Overlap Protection Circuit
For the supply input (VCC) of the ADP3413, a local bypass capacitor is recommended to reduce the noise and to supply some of the peak currents drawn. Use a 1 F, low ESR capacitor. Multilayer ceramic chip (MLCC) capacitors provide the best combination of low ESR and small size and can be obtained from the following vendors: Murata TaiyoYuden Tokin GRM235Y5V106Z16 EMK325F106ZF C23Y5V1C106ZP www.murata.com www.t-yuden.com www.tokin.com
Keep the ceramic capacitor as close as possible to the ADP3413.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor (CBST) and a Schottky diode, as shown in Figure 1. Selection of these components can be done after the high-side MOSFET has been chosen. The bootstrap capacitor must have a voltage rating that is able to handle the maximum battery voltage plus 5 volts. A minimum 50 V rating is recommended. The capacitance is determined using the following equation:
CBST = QGATE VBST
The Overlap Protection Circuit (OPC) prevents both of the main power switches, Q1 and Q2, from being ON at the same time. This is done to prevent shoot-through currents from flowing through both power switches and the associated losses that can occur during their ON-OFF transitions. The Overlap Protection Circuit accomplishes this by adaptively controlling the delay from Q1's turn OFF to Q2's turn ON, and by internally setting the delay from Q2's turn OFF to Q1's turn ON. To prevent the overlap of the gate drives during Q1's turn OFF and Q2's turn ON, the overlap circuit monitors the voltage at the SW pin. When the PWM input signal goes low, Q1 will begin to turn OFF (after a propagation delay), but before Q2 can turn ON the overlap protection circuit waits for the voltage at the SW pin to fall from VIN to 1 V. Once the voltage on the SW pin has fallen to 1 V, Q2 will begin turn ON. By waiting for the voltage on the SW pin to reach 1 V, the overlap protection circuit ensures that Q1 is OFF before Q2 turns on, regardless of variations in temperature, supply voltage, gate charge, and drive current. -6-
where, QGATE is the total gate charge of the high-side MOSFET, and VBST is the voltage droop allowed on the high-side MOSFET drive. For example, the IRF7811 has a total gate charge of about 20 nC. For an allowed droop of 200 mV, the required bootstrap capacitance is 100 nF. A good quality ceramic capacitor should be used. A Schottky diode is recommended for the bootstrap diode due to its low forward drop, which maximizes the drive available for the high-side MOSFET. The bootstrap diode must have a minimum 40 V rating to withstand the maximum battery voltage plus 5 V. The average forward current can be estimated by:
I F(AVG) QGATE x f MAX
where fMAX is the maximum switching frequency of the controller. The peak surge current rating should be checked in-circuit, since this is dependent on the source impedance of the 5 V supply, and the ESR of CBST. REV. 0
ADP3413
Printed Circuit Board Layout Considerations Typical Application Circuits
Use the following general guidelines when designing printed circuit boards: 1. 2. 3. Trace out the high-current paths and use short, wide traces to make these connections. Connect the PGND pin of the ADP3413 as close as possible to the source of the lower MOSFET. The VCC bypass capacitor should be located as close as possible to VCC and PGND pins.
The circuit in Figure 4 shows how two drivers can be combined with the ADP3160 to form a total power conversion solution for VCC(CORE) generation in a high-current Intel CPU computer. Figure 5 gives a similar application circuit for a 45 A AMD processor.
VIN 12V VINRTN
270 F 4 OS-CON 16V C12 C13 C14 C15
R7 20
R4 4m C26 4.7 F R5 2.4k C23 10 F D1 MBR052LTI C24 10 F C9 1F
R6 10
C21 15nF
C4 4.7 F
Z1 ZMM5236BCT
Q5 2N3904
1 2 3
U2 ADP3413
BST IN OD VCC DRVH 8 SW 7 PGND 6 DRVL 5 Q2 FDB8030L Q1 FDB7030L L1 600nH
U1 ADP3160
1
4
VID4 VID3 VID2 VID1 VID0 COMP
VCC 16 REF 15 CS- 14 PWM1 13 PWM2 12 CS+ 11
FROM CPU RA 34.0k COC 1.4nF RZ 1.1k RB 11.5k
C22 1nF
C5 1F
2 3 4 5 6 7 8
1200 F 8 OS-CON 2.5V 11m ESR (EACH) D2 MBR052LTI C10 1F + + + + + + + +
VCC(CORE) 1.1V - 1.85V 53.4A
FB PWRGND 10 CT GND
9
U3 ADP3413
1 2
C11 C16 C17 C18 C19 C20 C21 C22
VCC(CORE) RTN
C1 150pF
BST IN OD VCC
DRVH 8 SW 7 PGND 6 DRVL 5
Q3 FDB7030L
L2 600nH
C2 100pF
R1 1k C6 1F
3 4
Q4 FDB8030L
Figure 4. 53.4 A Intel CPU Supply Circuit
REV. 0
-7-
ADP3413
VIN 5V VINRTN 1000 F 6 RUBYCON ZA SERIES C12 C13 C14 C15 C24 C25 R7 20 R4 5m
12V VCC 12V VCCRTN R6 10
D1 MBR052LTI C21 15nF R5 2.4k Q5 2N3904
1 2 3
C9 1F
U2 ADP3413
BST IN OD VCC DRVH 8 SW 7 PGND 6 DRVL 5 Q2 FDB7045L Q1 FDB7030L L1 600nH
C4 4.7 F
Z1 ZMM5236BCT
U1 ADP3160
1
4
VID4 VID3 VID2 VID1 VID0 COMP FB CT
VCC 16 REF
15
FROM CPU RA 6.98k COC 4.7nF RZ 750 RB 14.0k
C22 1nF
C5 1F
2 3 4 5 6 7 8
CS- 14 PWM1 13 PWM2 12 CS+ 11 PWR 10 GND 9 D2 MBR052LTI C10 1F +
1000 F 8 RUBYCON ZA SERIES 24m ESR (EACH) + + + + + + +
VCC(CORE) 1.1V - 1.85V 45A
U3 ADP3413
1 2
C11 C16 C17 C18 C19 C20 C27 C28
VCC(CORE) RTN
C1 150pF
BST IN OD VCC
DRVH 8 SW 7 PGND 6 DRVL 5
Q3 FDB7030L
L2 600nH
C2 100pF
R1 1k C6 1F
3 4
Q4 FDB7045L
Figure 5. 45 A Athlon Duron CPU Supply Circuit
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Small Outline Package (R-8A)
PRINTED IN U.S.A.
0.1968 (5.00) 0.1890 (4.80)
8 5 4
0.1574 (4.00) 0.1497 (3.80) PIN 1
1
0.2440 (6.20) 0.2284 (5.80)
0.0500 (1.27) BSC 0.0098 (0.25) 0.0040 (0.10) SEATING PLANE 0.102 (2.59) 0.094 (2.39) 0.0192 (0.49) 0.0138 (0.35) 8 0.0098 (0.25) 0 0.0075 (0.19)
0.0196 (0.50) 0.0099 (0.25)
45
0.0500 (1.27) 0.0160 (0.41)
-8-
REV. 0
C02399-1-7/01(0)
C26 4.7 F
C29 10 F
C30 10 F

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