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M FEATURES 93C56A/B PACKAGE TYPE PDIP CS CLK DI DO 1 2 3 4 VCC 8 7 6 5 NC NC VSS 2K 5.0V Automotive Temperature Microwire(R) Serial EEPROM * Single supply 5.0V operation * Low power CMOS technology - 1 mA active current (typical) - 1 A standby current (maximum) * 256 x 8 bit organization (93C56A) * 128 x 16 bit organization (93C56B) * Self-timed ERASE and WRITE cycles (including auto-erase) * Automatic ERAL before WRAL * Power on/off data protection circuitry * Industry standard 3-wire serial interface * Device status signal during ERASE/WRITE cycles * Sequential READ function * 100,000 E/W cycles guaranteed * Data retention > 200 years * 8-pin PDIP and SOIC packages * Available for the following temperature ranges: - Automotive (E): -40C to +125C 93C56A/B SOIC CS CLK DI DO 1 8 VCC NC NC VSS 93C56A/B 2 3 4 7 6 5 BLOCK DIAGRAM MEMORY ARRAY ADDRESS DECODER DESCRIPTION The Microchip Technology Inc. 93C56A/B is a 2K-bit, low-voltage serial Electrically Erasable PROM. The device memory is configured as 256 x 8 bits (93C56A) or 128 x 16 bits (93C56B). Advanced CMOS technology makes this device ideal for low-power, nonvolatile memory applications. The 93C56A/B is available in standard 8-pin DIP and surface mount SOIC packages. This device is only recommeded for 5V automotive temperature applications. For all commercial and industrial applications, the 93LC56A/B is recommended. ADDRESS COUNTER DATA REGISTER DI MEMORY DECODE LOGIC CLOCK GENERATOR VCC VSS OUTPUT BUFFER DO CS CLK Microwire is a registered trademark of National Semiconductor. (c) 1998 Microchip Technology Inc. Preliminary DS21206B-page 1 93C56A/B 1.0 1.1 ELECTRICAL CHARACTERISTICS Maximum Ratings* TABLE 1-1: Name CS CLK DI DO VSS NC VCC PIN FUNCTION TABLE Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground No Connect Power Supply VCC ...................................................................................7.0V All inputs and outputs w.r.t. VSS ................ -0.6V to Vcc +1.0V Storage temperature .....................................-65C to +150C Ambient temp. with power applied.................-65C to +125C Soldering temperature of leads (10 seconds) ............. +300C ESD protection on all pins................................................4 kV *Notice: Stresses above those listed under "Maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-2: DC AND AC ELECTRICAL CHARACTERISTICS Automotive (E)VCC = +4.5V to +5.5VTamb = -40C to +125C All parameters apply over the specified operating ranges unless otherwise noted Parameter High level input voltage Low level input voltage Low level output voltage High level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Operating current Standby current Clock frequency Clock high time Clock low time Chip select setup time Chip select hold time Chip select low time Data input setup time Data input hold time Data output delay time Data output disable time Status valid time Program cycle time Endurance Symbol VIH VIL VOL VOH ILI ILO CIN, COUT ICC write ICC read ICCS FCLK TCKH TCKL TCSS TCSH TCSL TDIS TDIH TPD TCZ TSV TWC TEC TWL -- Min. 2.0 -0.3 -- 2.4 -10 -10 -- -- -- -- -- 250 250 50 0 250 100 100 -- -- -- -- -- -- 100K Max. VCC +1 0.8 0.4 -- 10 10 7 1.5 1 1 2 -- -- -- -- -- -- -- 400 100 500 2 6 15 -- Units V V V V A A pF mA mA A MHz ns ns ns ns ns ns ns ns ns ns ms ms ms cycles CS = VSS (Note 2) Conditions IOL = 2.1 mA; VCC = 4.5V IOH = -400 A; VCC = 4.5V VIN = VSS to VCC VOUT = VSS to VCC VIN/VOUT = 0 V (Notes 1 & 2) Tamb = +25C, FCLK = 1 MHz Relative to CLK Relative to CLK Relative to CLK Relative to CLK CL = 100 pF CL = 100 pF (Note 2) CL = 100 pF ERASE/WRITE mode ERAL mode WRAL mode 25C, VCC = 5.0V, Block Mode (Note 3) Note 1: This parameter is tested at Tamb = 25C and FCLK = 1 MHz. 2: This parameter is periodically sampled and not 100% tested. 3: This application is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which may be obtained on Microchip's BBS or website. DS21206B-page 2 Preliminary (c) 1998 Microchip Technology Inc. 93C56A/B 2.0 2.1 PIN DESCRIPTION Chip Select (CS) CLK cycles are not required during the self-timed WRITE (i.e., auto ERASE/WRITE) cycle. After detecting a START condition, the specified number of clock cycles (respectively low to high transitions of CLK) must be provided. These clock cycles are required to clock in all required opcode, address, and data bits before an instruction is executed (Table 2-1 and Table 2-2). CLK and DI then become don't care inputs waiting for a new START condition to be detected. Note: CS must go low between consecutive instructions. A high level selects the device. A low level deselects the device and forces it into standby mode. However, a programming cycle which is already in progress will be completed, regardless of the CS input signal. If CS is brought low during a program cycle, the device will go into standby mode as soon as the programming cycle is completed. CS must be low for 250 ns minimum (TCSL) between consecutive instructions. If CS is low, the internal control logic is held in a RESET status. 2.3 Data In (DI) 2.2 Serial Clock (CLK) The Serial Clock is used to synchronize the communication between a master device and the 93C56A/B. Opcode, address, and data bits are clocked in on the positive edge of CLK. Data bits are also clocked out on the positive edge of CLK. CLK can be stopped anywhere in the transmission sequence (at high or low level) and can be continued anytime with respect to clock high time (TCKH) and clock low time (TCKL). This gives the controlling master freedom in preparing opcode, address, and data. CLK is a "Don't Care" if CS is low (device deselected). If CS is high, but the START condition has not been detected, any number of clock cycles can be received by the device without changing its status (i.e., waiting for a START condition). Data In is used to clock in a START bit, opcode, address, and data synchronously with the CLK input. 2.4 Data Out (DO) Data Out is used in the READ mode to output data synchronously with the CLK input (TPD after the positive edge of CLK). This pin also provides READY/BUSY status information during ERASE and WRITE cycles. READY/BUSY status information is available on the DO pin if CS is brought high after being low for minimum chip select low time (TCSL) and an ERASE or WRITE operation has been initiated. The status signal is not available on DO, if CS is held low during the entire ERASE or WRITE cycle. In this case, DO is in the HIGH-Z mode. If status is checked after the ERASE/WRITE cycle, the data line will be high to indicate the device is ready. . TABLE 2-1: ERASE ERAL EWDS EWEN READ WRITE WRAL 1 1 1 1 1 1 1 INSTRUCTION SET FOR 93C56A Address X 1 0 1 X X 0 A7 0 0 1 A7 A7 1 A6 X X X A6 A6 X A5 X X X A5 A5 X A4 X X X A4 A4 X A3 X X X A3 A3 X A2 X X X A2 A2 X A1 X X X A1 A1 X A0 X X X A0 A0 X Instruction SB Opcode 11 00 00 00 10 01 00 Data In -- -- -- -- -- D7 - D0 D7 - D0 Data Out (RDY/BSY) (RDY/BSY) HIGH-Z HIGH-Z D7 - D0 (RDY/BSY) (RDY/BSY) Req. CLK Cycles 12 12 12 12 20 20 20 TABLE 2-2: ERASE ERAL EWDS EWEN READ WRITE WRAL 1 1 1 1 1 1 1 INSTRUCTION SET FOR 93C56B Address X 1 0 1 X X 0 A6 0 0 1 A6 A6 1 A5 X X X A5 A5 X A4 X X X A4 A4 X A3 X X X A3 A3 X A2 X X X A2 A2 X A1 X X X A1 A1 X A0 X X X A0 A0 X Instruction SB Opcode 11 00 00 00 10 01 00 Data In -- -- -- -- -- D15 - D0 D15 - D0 Data Out (RDY/BSY) (RDY/BSY) HIGH-Z HIGH-Z D15 - D0 (RDY/BSY) (RDY/BSY) Req. CLK Cycles 11 11 11 11 27 27 27 (c) 1998 Microchip Technology Inc. Preliminary DS21206B-page 4-3 93C56A/B 3.0 FUNCTIONAL DESCRIPTION 3.2 Data IN (DI) and Data Out (DO) Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (CLK). The DO pin is normally held in a HIGH-Z state except when reading data from the device, or when checking the READY/BUSY status during a programming operation. The READY/BUSY status can be verified during an ERASE/WRITE operation by polling the DO pin; DO low indicates that programming is still in progress, while DO high indicates the device is ready. The DO will enter the HIGH-Z state on the falling edge of the CS. It is possible to connect the Data In (DI) and Data Out (DO) pins together. However, with this configuration, if A0 is a logic-high level, it is possible for a "bus conflict" to occur during the "dummy zero" that precedes the READ operation. Under such a condition, the voltage level seen at DO is undefined and will depend upon the relative impedances of DO and the signal source driving A0. The higher the current sourcing capability of A0, the higher the voltage at the DO pin. 3.1 START Condition 3.3 Data Protection The START bit is detected by the device if CS and DI are both high with respect to the positive edge of CLK for the first time. Before a START condition is detected, CS, CLK, and DI may change in any combination (except to that of a START condition), without resulting in any device operation (READ, WRITE, ERASE, EWEN, EWDS, ERAL, and WRAL). As soon as CS is high, the device is no longer in the standby mode. An instruction following a START condition will only be executed if the required amount of opcode, address and data bits for any particular instruction is clocked in. After execution of an instruction (i.e., clock in or out of the last required address or data bit) CLK and DI become don't care bits until a new START condition is detected. During power-up, all programming modes of operation are inhibited until Vcc has reached a level greater than 3.8V. During power-down, the source data protection circuitry acts to inhibit all programming modes when Vcc has fallen below 3.8V at nominal conditions. The ERASE/WRITE Disable (EWDS) and ERASE WRTE Enable (EWEN) commands give additional protection against accidentally programming during normal operation. After power-up, the device is automatically in the EWDS mode. Therefore, an EWEN instruction must be performed before any ERASE or WRITE instruction can be executed. FIGURE 3-1: CS SYNCHRONOUS DATA TIMING VIH VIL VIH TCSS TCKH TCKL TCSH CLK VIL TDIS VIH TDIH DI VIL TPD TPD TCZ DO (READ) DO (PROGRAM) Note: VOH VOL TSV VOH TCZ STATUS VALID VOL AC Test Conditions: VIL = 0.4V, VIH = 2.4V. DS21206B-page 4 Preliminary (c) 1998 Microchip Technology Inc. 93C56A/B 3.4 ERASE 3.5 Erase All (ERAL) The ERASE instruction forces all data bits of the specified address to the logical "1" state. This cycle begins on the rising clock edge of the last address bit. The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (TCSL). DO at logical "0" indicates that programming is still in progress. DO at logical "1" indicates that the register at the specified address has been erased and the device is ready for another instruction. The ERAL instruction will erase the entire memory array to the logical "1" state. The ERAL cycle is identical to the ERASE cycle, except for the different opcode. The ERAL cycle is completely self-timed and commences at the rising clock edge of the last address bit. Clocking of the CLK pin is not necessary after the device has entered the ERAL cycle. The DO pin indicates the READY/BUSY status of the device, if CS is brought high after a minimum of 250 ns low (TCSL) and before the entire ERAL cycle is complete. FIGURE 3-2: CS ERASE TIMING TCSL CHECK STATUS CLK DI 1 1 1 AN AN-1 AN-2 *** A0 TSV TCZ READY HIGH-Z TWC DO HIGH-Z BUSY FIGURE 3-3: CS ERAL TIMING TCSL CHECK STATUS CLK DI 1 0 0 1 0 X *** X TSV TCZ READY HIGH-Z TEC DO HIGH-Z BUSY (c) 1998 Microchip Technology Inc. Preliminary DS21206B-page 5 93C56A/B 3.6 ERASE/WRITE Disable and Enable (EWDS/EWEN) 3.7 READ The READ instruction outputs the serial data of the addressed memory location on the DO pin. A dummy zero bit precedes the 8-bit (93C56A) or 16-bit (93C56B) output string. The output data bits will toggle on the rising edge of the CLK and are stable after the specified time delay (TPD). Sequential read is possible when CS is held high. The memory data will automatically cycle to the next register and output sequentially. The device powers up in the ERASE/WRITE Disable (EWDS) state. All programming modes must be preceded by an ERASE/WRITE Enable (EWEN) instruction. Once the EWEN instruction is executed, programming remains enabled until an EWDS instruction is executed or VCC is removed from the device. To protect against accidental data disturbance, the EWDS instruction can be used to disable all ERASE/WRITE functions and should follow all programming operations. Execution of a READ instruction is independent of both the EWEN and EWDS instructions. FIGURE 3-4: CS READ TIMING CLK DI 1 1 0 An *** A0 DO HIGH-Z 0 Dx *** D0 Dx *** D0 Dx *** D0 FIGURE 3-5: CS EWDS TIMING TCSL CLK DI 1 0 0 0 0 X *** X FIGURE 3-6: EWEN TIMING TCSL CS CLK DI 1 0 0 1 1 X *** X DS21206B-page 6 Preliminary (c) 1998 Microchip Technology Inc. 93C56A/B 3.8 WRITE 3.9 Write All (WRAL) The WRITE instruction is followed by 8-bits (93C56A) 16-bits (93C56B) of data which are written into the specified address. After the last data bit is clocked into the DI pin, the self-timed auto-erase and programming cycle begins. The DO pin indicates the READY/BUSY status of the device, if CS is brought high after a minimum of 250 ns low (TCSL) and before the entire write cycle is complete. DO at logical "0" indicates that programming is still in progress. DO at logical "1" indicates that the register at the specified address has been written with the data specified and the device is ready for another instruction. The Write All (WRAL) instruction will write the entire memory array with the data specified in the command. The WRAL cycle is completely self-timed and commences at the rising clock edge of the last data bit. Clocking of the CLK pin is not necessary after the device has entered the WRAL cycle. The WRAL command does include an automatic ERAL cycle for the device. Therefore, the WRAL instruction does not require an ERAL instruction but the chip must be in the EWEN status. The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (TCSL). FIGURE 3-7: CS WRITE TIMING TCSL CLK DI 1 0 1 An *** A0 Dx *** D0 TSV TCZ READY DO HIGH-Z BUSY HIGH-Z Twc FIGURE 3-8: CS WRAL TIMING TCSL CLK DI 1 0 0 0 1 X *** X Dx *** D0 TSV TCZ DO HIGH-Z BUSY READY HIGH-Z TWL (c) 1998 Microchip Technology Inc. Preliminary DS21206B-page 7 93C56A/B NOTES: DS21206B-page 8 Preliminary (c) 1998 Microchip Technology Inc. 93C56A/B NOTES: (c) 1998 Microchip Technology Inc. Preliminary DS21206B-page 9 93C56A/B NOTES: DS21206B-page 10 Preliminary (c) 1998 Microchip Technology Inc. 93C56A/B 93C56A/B PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. 93C56A/B /P Package: P = Plastic DIP (300 mil Body), 8-lead SN = Plastic SOIC (150 mil Body), 8-lead E = -40C to +125C Temperature Range: 93C56A Device: 93C56AT 93C56B 93C56BT 2K Microwire Serial EEPROM (x8) 2K Microwire Serial EEPROM (x8) Tape and Reel 2K Microwire Serial EEPROM (x16) 2K Microwire Serial EEPROM (x16) Tape and Reel Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office. 2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277. 3. The Microchip's Bulletin Board, via your local CompuServe number (CompuServe membership NOT required). (c) 1998 Microchip Technology Inc. Preliminary DS21206B-page 11 M WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602-786-7200 Fax: 602-786-7277 Technical Support: 602 786-7627 Web: http://www.microchip.com ASIA/PACIFIC Hong Kong Microchip Asia Pacific RM 3801B, Tower Two Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2-401-1200 Fax: 852-2-401-3431 EUROPE United Kingdom Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44-1189-21-5858 Fax: 44-1189-21-5835 Atlanta Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307 India Microchip Technology Inc. India Liaison Office No. 6, Legacy, Convent Road Bangalore 560 025, India Tel: 91-80-229-0061 Fax: 91-80-229-0062 France Arizona Microchip Technology SARL Zone Industrielle de la Bonde 2 Rue du Buisson aux Fraises 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Boston Microchip Technology Inc. 5 Mount Royal Avenue Marlborough, MA 01752 Tel: 508-480-9990 Fax: 508-480-8575 Korea Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea Tel: 82-2-554-7200 Fax: 82-2-558-5934 Germany Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 Muchen, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44 Chicago Microchip Technology Inc. 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075 Italy Arizona Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-39-6899939 Fax: 39-39-6899883 Shanghai Microchip Technology RM 406 Shanghai Golden Bridge Bldg. 2077 Yan'an Road West, Hong Qiao District Shanghai, PRC 200335 Tel: 86-21-6275-5700 Fax: 86 21-6275-5060 Dallas Microchip Technology Inc. 14651 Dallas Parkway, Suite 816 Dallas, TX 75240-8809 Tel: 972-991-7177 Fax: 972-991-8588 Singapore Microchip Technology Taiwan Singapore Branch 200 Middle Road #07-02 Prime Centre Singapore 188980 Tel: 65-334-8870 Fax: 65-334-8850 Dayton Microchip Technology Inc. Two Prestige Place, Suite 150 Miamisburg, OH 45342 Tel: 937-291-1654 Fax: 937-291-9175 JAPAN Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa 222 Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122 12/30/97 Los Angeles Microchip Technology Inc. 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 714-263-1888 Fax: 714-263-1338 Taiwan, R.O.C Microchip Technology Taiwan 10F-1C 207 Tung Hua North Road Taipei, Taiwan, ROC Tel: 886-2-2717-7175 Fax: 886-2-2545-0139 New York Microchip Technology Inc. 150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 516-273-5305 Fax: 516-273-5335 San Jose Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955 Toronto Microchip Technology Inc. 5925 Airport Road, Suite 200 Mississauga, Ontario L4V 1W1, Canada Tel: 905-405-6279 Fax: 905-405-6253 All rights reserved. (c) 1998, Microchip Technology Incorporated, USA. 1/98 Printed on recycled paper. Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. DS21206B-page 12 Preliminary (c) 1998 Microchip Technology Inc. |
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