| PART |
Description |
Maker |
| CY7C1625KV18 CY7C1614KV18 |
144-Mbit QDR? II SRAM Two-Word Burst Architecture
|
Cypress Semiconductor
|
| CY7C1474V33-167BGC CY7C1470V33-250AXC CY7C1470V33- |
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture
ECONOLINE: RQS & RQD - 1kVDC Isolation- Internal SMD Construction- UL94V-0 Package Material- Toroidal Magnetics- Efficiency to 80%
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture 4M X 18 ZBT SRAM, 3 ns, PBGA165
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture 4M X 18 ZBT SRAM, 3.4 ns, PBGA165
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture 1M X 72 ZBT SRAM, 3.4 ns, PBGA209
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture 2M X 36 ZBT SRAM, 3.4 ns, PBGA165
|
Cypress Semiconductor Corp.
Cypress Semiconductor, Corp.
|
| CY7C1668KV18-450BZXC CY7C1668KV18-550BZXC |
144-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
|
Cypress
|
| R1QDA4418RBG-18IA0 R1QDA4436RBG-20IB0 |
144-Mbit QDR?II SRAM 4-word Burst Architecture (2.5 Cycle Read latency) with ODT
144-Mbit QDR?II SRAM 4-word Burst Architecture (2.5 Cycle Read latency) with ODT
|
Renesas Electronics Corporation
|
| M48Z2M1Y10 M48Z2M1V-85PL1 M48Z2M1Y-85PL1 M48Z2M1Y- |
5 V or 3.3 V, 16 Mbit (2 Mb x 8) ZEROPOWER庐 SRAM
5 V or 3.3 V, 16 Mbit (2 Mb x 8) ZEROPOWER? SRAM
2M X 8 NON-VOLATILE SRAM MODULE, 70 ns, PDIP36
|
STMicroelectronics
|
| BBS-15 BBS-1/4 BBS-2/10 BBS-1-8/10 BBS-10 BBS-1-6/ |
72-Mbit QDR™-II SRAM 2-Word Burst Architecture
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture
72-Mbit DDR-II SRAM 2-Word Burst Architecture
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture
36-Mbit QDR™-II SRAM 4-Word Burst Architecture
Fuse
256K (32K x 8) Static RAM
64/256/512/1K/2K/4K x 18 Synchronous FIFOs
Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
Neuron® Chip Network Processor
64-Kbit (8K x 8) Static RAM
72-Mbit QDR™-II SRAM 2-Word Burst Architecture 保险
|
NXP Semiconductors N.V.
|
| CAT64LC20ZS CAT64LC20ZP CAT64LC20J-TE7 CAT64LC20J- |
36-Mbit QDR™-II SRAM 4-Word Burst Architecture
36-Mbit QDR™-II SRAM 2-Word Burst Architecture
9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL™ Architecture
4-Mbit (128K x 36) Pipelined SRAM with NoBL™ Architecture
4-Mbit (128K x 36) Flow-through SRAM with NoBL™ Architecture
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL™ Architecture
SPI Serial EEPROM SPI串行EEPROM
36-Mbit QDR™-II SRAM 2-Word Burst Architecture SPI串行EEPROM
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM SPI串行EEPROM
256K (32K x 8) Static RAM SPI串行EEPROM
|
Analog Devices, Inc.
Electronic Theatre Controls, Inc.
|
| SST31LF021-300-4E-WH SST31LF021E-300-4E-WH SST31LF |
2 Mbit Flash 1 Mbit SRAM ComboMemory SPECIALTY MEMORY CIRCUIT, PDSO32
2 Mbit Flash 1 Mbit SRAM ComboMemory 2 Mbit闪存1兆位的SRAM ComboMemory
|
Silicon Storage Technology, Inc.
|
| M3H71FAD-R M3H15TDD M3H52TCD-R MH75FBD MH75FAG MH7 |
8 pin DIP, 3.3 or 5.0 Volt, HCMOS/TTL Clock Oscillator
16-bit, 75 MIPS, 2.5v, 2 serial ports, host port, 80 KB RAM; Package: 144 ball CSPBGA (10x10x1.4mm); No of Pins: 144; Temperature Range: Ind
16-Bit, 80MIPS, 1.8V, 2 Serial Ports, Host Port, 20KB RAM; Package: 144 ball CSPBGA (10x10x1.4mm); No of Pins: 144; Temperature Range: Comm.
16-Bit, 80MIPS, 1.8V, 2 Serial Ports, Host Port, 80KB RAM; Package: 144 ball CSPBGA (10x10x1.4mm); No of Pins: 144; Temperature Range: Ind
16-Bit, 80MIPS, 1.8V, 2 Serial Ports, Host Port, 80KB RAM; Package: 144 ball CSPBGA (10x10x1.4mm); No of Pins: 144; Temperature Range: Comm.
16-Bit, 75 MIPS, 2.5V, 2 Serial Ports, Host Port, 40 KB RAM; Package: 144 ball CSPBGA (10x10x1.4mm); No of Pins: 144; Temperature Range: Comm.
500 MHz TigerSHARC Processor with 12 Mbit on-chip embedded DRAM; Package: 576 ball SBGA; No of Pins: 576; Temperature Range: Ind
300 MHz TigerSHARC Processor with 6 Mbit on-chip SRAM; Package: 625 ball BGA; No of Pins: 625; Temperature Range: Ind
500 MHz TigerSHARC Processor with 12 Mbit on-chip embedded DRAM; Package: BGA THERM ENH W/ HEATSINK; No of Pins: 576; Temperature Range: Ind
300 MHz TigerSHARC Processor with 6 Mbit on-chip SRAM; Package: 484 ball BGA; No of Pins: 484; Temperature Range: Ind
8 pin DIP, 3.3 or 5.0 Volt, HCMOS/TTL Clock Oscillator
|
MTRONPTI
|
| CY7C1474V33-200BGI CY7C1472V33-250BZXI CY7C1470V33 |
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBLArchitecture 1M X 72 ZBT SRAM, 3 ns, PBGA209
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBLArchitecture 4M X 18 ZBT SRAM, 3 ns, PBGA165
2M X 36 ZBT SRAM, 3 ns, PQFP100
|
Cypress Semiconductor, Corp.
CYPRESS SEMICONDUCTOR CORP
|
