PART |
Description |
Maker |
ADLE3800SEC-E3827 ADLE3800SEC-E3845 |
Edge-Connect Architecture
|
ADL Embedded Solutions
|
ADLSEC-1710 |
Edge-Connect Architecture
|
ADL Embedded Solutions
|
YGV641 |
Cutting-edge GDC with Sprite Architecture
|
YAMAHA CORPORATION
|
M5-128/120-5YI M5-128/120-5YC M5-128/160-5YI M5-19 |
Fifth Generation MACH Architecture 第五代马赫架 Fifth Generation MACH Architecture EE PLD, 15 ns, PQFP160 Fifth Generation MACH Architecture EE PLD, 10 ns, PQFP160 Fifth Generation MACH Architecture EE PLD, 7.5 ns, PQFP208 Fifth Generation MACH Architecture EE PLD, 5.5 ns, PQFP100 Fifth Generation MACH Architecture EE PLD, 12 ns, PQFP208 Fifth Generation MACH Architecture EE PLD, 7.5 ns, PQFP160 Fifth Generation MACH Architecture EE PLD, 12 ns, PBGA256 Fifth Generation MACH Architecture EE PLD, 12 ns, PQFP100 Fifth Generation MACH Architecture EE PLD, 15 ns, PBGA352
|
Lattice Semiconductor Corporation Lattice Semiconductor, Corp. Air Cost Control
|
CY7C1561KV18 CY7C1561KV18-400BZC CY7C1561KV18-400B |
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: QDR-II , 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 4M X 18 QDR SRAM, 0.29 ns, PBGA165 72-Mbit QDR-II SRAM 4-Word Burst Architecture
|
Cypress Semiconductor, Corp.
|
CAT64LC10ZJ CAT64LC10ZP CAT64LC10J-TE7 CAT64LC10J- |
18-Mbit QDR-II SRAM 4-Word Burst Architecture 18-Mbit DDR-II SRAM 2-Word Burst Architecture 36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) 4-Mbit (256K x 18) Flow-Through Sync SRAM SPI串行EEPROM SPI Serial EEPROM SPI串行EEPROM
|
Analog Devices, Inc.
|
CY7C1518JV18-250BZC CY7C1518JV18-300BZXC |
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 4M X 18 DDR SRAM, 0.45 ns, PBGA165
|
Cypress Semiconductor, Corp.
|
CAT93C46AJ CAT93C46AJI CAT93C46AJI-2.5 CAT93C46AJ- |
72-Mbit QDR-II SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) 72-Mbit QDR-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) 72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) 256K (32K x 8) Static RAM 256 Kb (256K x 1) Static RAM 72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) Microwire Serial EEPROM 微型导线串行EEPROM
|
Atmel, Corp.
|
CY7C1470V25-167AXC CY7C1470V25-167AXI CY7C1470V25- |
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL垄芒 Architecture 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture
|
Cypress Semiconductor
|
CY7C1307AV18-167BZC CY7C1307AV18 CY7C1307AV18-100B |
18-Mb Burst of 4 Pipelined SRAM with QDR垄芒 Architecture 18-Mb Burst of 4 Pipelined SRAM with QDR Architecture
|
Cypress Semiconductor
|
CY7C1514V18 CY7C1514V18-200BZC CY7C1514V18-250BZC |
72-Mbit QDR-II?SRAM 2-Word Burst Architecture 72-Mbit QDR-II(TM) SRAM 2-Word Burst Architecture 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture 72-MBIT QDR-II⒙ SRAM 2-WORD BURST ARCHITECTURE 72-Mbit QDR-II SRAM 2-Word Burst Architecture
|
CYPRESS[Cypress Semiconductor]
|