| PART |
Description |
Maker |
| NB6L16D NB6L16DTR2G NB6L16 NB6L16DG NB6L16DR2 NB6L |
2.5V/3.3V Multilevel Input to Differential LVPECL/LVNECL Clock or Data Receiver/Driver/Translator Buffer(2.5V/3.3V多级输入到差分LVPECL/LVNECL时钟或数据输出接收器/驱动
2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL Clock or Data Receiver/Driver/Translator Buffer
|
ONSEMI[ON Semiconductor]
|
| NB6L16 |
6GHz/6Gbps 2.5V/3.3V Multi-level Input to Differential Lvecl Clock or Data Translator/receiver/driver Buffer
|
ON Semiconductor
|
| NB7L216MNR2 NB7L216MNR2G NB7L216MNG NB7L216 NB7L21 |
2.5V/3.3V, 12Gb/s Multi Level Clock/Data Input to RSECL, High Gain Receiver/Buffer/Translator with Internal Termination
|
ONSEMI[ON Semiconductor]
|
| AD802 AD800 AD800-52BR AD800-45BQ AD802-155BR AD80 |
Clock Recovery and Data Retiming Phase-Locked Loop
Clock Recovery and Data Retiming Phase-Locked Loop PHASE LOCKED LOOP, PDSO20
Clock Recovery and Data Retiming Phase-Locked Loop(时钟恢复和重定时PLL)
AD800/AD802: Clock Recovery and Data Retiming Phase-Locked Loop Data Sheet (Rev. B. 12/93)
45 or 52 Mbps Clock and Data Recovery IC
|
Analog Devices, Inc.
|
| SL6649-1 SL6649-KG SL6649-I SL6649-MPEF SL6649-MPE |
200MHz Direct Conversion Downstream Keying (DSK) Data Receiver
200MHz DIRECT CONVERSION FSK DATA RECEIVER 200MHz的直接转换接收FSK数据
|
Zarlink Semiconductor Inc.
Zarlink Semiconductor, Inc.
|
| NB7L216 |
2.5V/3.3V, 12Gb/s Multi Level Clock/Data Input to RSECL, High Gain Receiver/Buffer/Translator with Internal Termination(带内部端口的2.5V/3.3V,12Gb/s多级时钟/数据输入到RSECL,高增益接收器/缓冲转换
|
ON Semiconductor
|
| SRM-155 SRM-155A SRM-155B SRM-155C |
Telecomm/Datacomm
SONET/SDH Fiber-Optic Receiver Module with SAW Filter Clock Recovery and Data Retiming(SONET/SDH 光纤接收模块(带SAW滤波时钟恢复和数据重定时功能))
|
Vectron International, Inc.
|
| ADN2819ACPZ-CML-RL1 ADN2819ACP-CML ADN2819 EVAL-AD |
Multi Rate Limiting Amplifier and Clock and Data Recovery ICs
Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp
N/A
|
AD[Analog Devices]
|
| ADN2811ACP-CML ADN2811 |
Dual Rate Limiting Amplifier and Clock and Data Recovery IC
OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp
|
Analog Devices, Inc.
|
| MC10H106 MC100EL29DWR2 MC10H117 MC10H117FN MC100EP |
Triple 4-3-3-Input NOR Gate
5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset
Dual 2-Wide 2-3-Input OR-AND/OR-AND-Invert Gate
3.3V / 5V ECL Differential Receiver/Driver with Variable Output Swing
5V ECL 2-Input XOR/XNOR
4-Wide OR-AND/OR-ANDbar Gate
5V ECL 1:2 Differential Fanout Buffer
3.3V / 5V ECL 6-Bit Differential Register with Master Reset
3.3V ECL Triple D-Type Flip-Flop with Set and Reset
3.3V / 5V ECL ÷2 Divider
5V ECL Differential Data and Clock D Flip-Flop
|
ON Semiconductor
|
| M13S2561616A-2S |
Double-data-rate architecture, two data transfers per clock cycle
|
Elite Semiconductor Mem...
|
