| PART |
Description |
Maker |
| IR1150LS |
uPFC One Cycle Control PFC IC
|
International Rectifier
|
| U6084B U6084B-FP |
PWM Power Control with Automatic Duty-cycle Reduction
|
ATMEL[ATMEL Corporation]
|
| U6081B |
PWM Power Control with Low Duty Cycle Switch Off
|
TEMIC[TEMIC Semiconductors]
|
| IR1150 IR1150PBF IR1150ISTRPBF |
One Cycle Control PFC IC designed to operate in continuous conduction mode (CCM), designed and qualified for the Consumer market
One Cycle Control PFC IC designed to operate in continuous conduction mode (CCM), designed and qualified for the Industrial market.
|
International Rectifier
|
| A67L7332SERIES A67L7336SERIES A67L8316SERIES A67L8 |
Cycle time:7ns; access time:4.5ns; 256K x 16 LVTTL, pipelined DBA SRAM
Cycle time:7ns; access time:4ns; 256K x 16 LVTTL, pipelined DBA SRAM
Cycle time:7ns; access time:4.2ns; 256K x 16 LVTTL, pipelined DBA SRAM
Cycle time:7ns; access time:4.2ns; 128K x 32 LVTTL, pipelined DBA SRAM
Cycle time:7ns; access time:4ns; 128K x 32 LVTTL, pipelined DBA SRAM
256K X 16/18. 128K X 32/36 LVTTL. Pipelined DBA SRAM 256 × 16/18128K的X 32/36 LVTTL等级。流水线数据库管理员的SRAM
256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM
Cycle time:7ns; access time:4.5ns; 128K x 32 LVTTL, pipelined DBA SRAM
Cycle time:7.5ns; access time:4.2ns; 128K x 32 LVTTL, pipelined DBA SRAM
Cycle time:8.5ns; access time:4.5ns; 128K x 32 LVTTL, pipelined DBA SRAM
|
AMIC Technology, Corp.
|
| A43L2616V-6PH A43L2616V-7PH |
Cycle time:6ns; 166MHz CL=3 access time:5.0ns 1M x 16bit x 4banks synchronous DRAM
Cycle time:7ns; 143MHz CL=3 access time:5.4ns 1M x 16bit x 4banks synchronous DRAM
|
AMIC Technology
|
| PTE5100D1A PTE5015D1A |
Sensorless control object code license for AC permanent magnet motor
Complete AC servo motor control IC one-chip solution for complete closed loop current control and velocity control for a high performance servo drive system. DIFFERENZDRUCKSENSOR
|
Sony, Corp.
|
| IS61LPD51218T/D IS61LPD25632T/D IS61SPD25632T/D IS |
256K x 32, 256K x 36, 512K x 18 SYNCHRONOUS PIPELINE, DOUBLE-CYCLE DESELECT STATIC RAM 256K × 3256K × 3612K采样× 18 SYNCHRONOU?管道，双循环取消选择静态RAM
256K X 36 CACHE SRAM, 3.5 ns, PQFP100 TQFP-100
256K x 32/ 256K x 36/ 512K x 18 SYNCHRONOUS PIPELINE/ DOUBLE-CYCLE DESELECT STATIC RAM
|
Integrated Silicon Solution, Inc.
Integrated Silicon Solution Inc
|
| CY7C1561V18-333BZC CY7C1561V18-333BZI CY7C1563V18 |
72-Mbit QDR垄芒-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
72-Mbit QDR?II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
|
Cypress Semiconductor
|
| IDT71V3577S75PFG IDT71V3577SA80PFGI IDT71V3577SA85 |
3.3V 128K x 36 Synchronous Flow-Through SRAM w/3.3V I/O
128K X 36, 256K X 18 3.3V Synchronous SRAMs 3.3V I/O, Flow-Through Outputs Burst Counter, Single Cycle Deselect 128K的米656 × 18 3.3同步SRAM.3VI / O的流量，通过输出脉冲计数器，单周期取
128K X 36, 256K X 18 3.3V Synchronous SRAMs 3.3V I/O, Flow-Through Outputs Burst Counter, Single Cycle Deselect 256K X 18 CACHE SRAM, 7.5 ns, PQFP100
128K X 36, 256K X 18 3.3V Synchronous SRAMs 3.3V I/O, Flow-Through Outputs Burst Counter, Single Cycle Deselect 128K X 36 CACHE SRAM, 7.5 ns, PQFP100
128K X 36, 256K X 18 3.3V Synchronous SRAMs 3.3V I/O, Flow-Through Outputs Burst Counter, Single Cycle Deselect 128K的米656 × 18 3.3同步SRAM.3V的I / O的流量，通过输出脉冲计数器，单周期取
128K X 36, 256K X 18 3.3V Synchronous SRAMs 3.3V I/O, Flow-Through Outputs Burst Counter, Single Cycle Deselect 256K X 18 CACHE SRAM, 8 ns, PBGA165
|
IDT
Integrated Device Technology, Inc.
INTEGRATED DEVICE TECHNOLOGY INC
Integrated Device Techn...
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