| PART |
Description |
Maker |
| TSOP7000SW1 |
IR Receiver for High Data Rate PCM at 455 kHz
|
VAISH[Vaishali Semiconductor]
|
| TSOP5700 |
IR Receiver for High Data Rate PCM at 455 kHz
|
VISAY[Vishay Siliconix]
|
| HDMP-1032 HDMP-1034 |
1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate
|
Agilent(Hewlett-Packard)
|
| IDT5T9050PGI IDT5T9050 |
2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFERJR 2.5V的单数据传输速率1:5时钟缓冲器TERABUFFER⑩JR
2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER⑩ JR
2.5V Single Data Rate 1:5 Clock Buffer Terabuffer Jr.
|
Integrated Device Technology, Inc.
IDT[Integrated Device Technology]
|
| HA7-2840883 FN3594 HA1-2840_883 HA1-2840883 HA7-28 |
From old datasheet system
Very High Slew Rate Wideband Operational Amplifier
Very High Slew Rate/ Wideband Operational Amplifier
Very High Slew Rate,
Wideband Operational Amplifier(高转换率、宽带运算放大器)
Very High Slew Rate, Wideband Operational Amplifier 甚高摆率，宽带运算放大器
Very High Slew Rate, Wideband Operational Amplifier OP-AMP, 6000 uV OFFSET-MAX, 500 MHz BAND WIDTH, CDIP14
|
INTERSIL[Intersil Corporation]
Intersil, Corp.
|
| W9725G6JB25I |
Double Data Rate architecture: two data transfers per clock cycle
|
Winbond
|
| W9751G6KB-18 W9751G6KB-25 W9751G6KB-3 W9751G6KB25A |
Double Data Rate architecture: two data transfers per clock cycle
|
Winbond
|
| M13L2561616A-2A |
Double-data-rate architecture, two data transfers per clock cycle
|
Elite Semiconductor Mem...
|
| M14D5121632A-2K |
Internal pipelined double-data-rate architecture; two data access per clock cycle
|
Elite Semiconductor Mem...
|
| M14D2561616A-2E |
Internal pipelined double-data-rate architecture; two data access per clock cycle
|
Elite Semiconductor Mem...
|
| DSK4D263238D K4D263238D K4D263238D-QC40 K4D263238D |
1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL
|
SAMSUNG SEMICONDUCTOR CO. LTD.
Samsung Electronic
SAMSUNG[Samsung semiconductor]
|
