| PART |
Description |
Maker |
| HCTS112MS HCTS112D HCTS112DMSR HCTS112HMSR HCTS112 |
Radiation Hardened Dual JK Flip-Flop HCT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC16
|
Intersil, Corp.
INTERSIL[Intersil Corporation]
|
| SN74LS377D SN74LS377N SN74LS379D SN74LS379DW SN74L |
OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE LS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16
OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE LS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20
OCTAL D FLIP-FLOP WITH ENABLE HEX D FLIP-FLOP WITH ENABLE 4-BIT D FLIP-FLOP WITH ENABLE
|
Motorola Mobility Holdings, Inc.
MOTOROLA[Motorola, Inc]
|
| 74AUP2G80GT 74AUP2G80GM 74AUP2G80DC 74AUP2G80 74AU |
Low-power dual D-type flip-flop; positive-edge trigger; Package: SOT833-1 (XSON8U); Container: Reel Pack, SMD, 7" AUP/ULP/V SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO8
|
PHILIPS[Philips Semiconductors]
NXP Semiconductors N.V.
|
| MC74HC76 MC74HC76D MC74HC76N ON1498 |
From old datasheet system
DUAL JK FLIP-FLOP WITH SER AND RESET
Dual JK Flip-Flop With Set and Reset
|
MOTOROLA[Motorola, Inc]
ON Semi
|
| MC74HC109 ON1335 |
Dual J-K Flip-Flop with Set and Rest
From old datasheet system
DUAL J-K FLIP-FLOP WITH SET AND RESET
|
Motorola, Inc
ON Semi
|
| 57401AJ/883B C57401AJ/883B 57401J 57401L 57402J 57 |
DUAL 'D' - TYPE FLIP-FLOP
x5 Asynchronous FIFO
7 STAGE RIPPLE-CARRY BINARY COUNTER/DIVIDERS
QUAD BILATERAL SWITCH
DUAL-J-K MASTER-SLAVE FLIP-FLOP X5的异步FIFO
x4 Asynchronous FIFO x4异步FIFO
|
Atmel, Corp.
NIC Components, Corp.
|
| 74ALS109AN 74ALS109A 74ALS109AD |
Dual J-K positive edge-triggered flip-flop with set and reset ALS SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16
|
Rochester Electronics, LLC
PHILIPS[Philips Semiconductors]
NXP Semiconductors
|
| MC10H131FNG MC10H131FN MC10H13106 MC10H135FNG MC10 |
Dual D Type Master?Slave Flip?Flop
Dual D Type Master−Slave Flip−Flop
Dual J?K Master?Slave Flip?Flop
Universal Hexadecimal Counter
Four?Bit Universal Shift Register
Quad 2?Input Multiplexer (Non?Inverting)
12?Bit Parity Generator?Checker
Binary to 1?8 Decoder (Low)
Binary to 1?8 Decoder (High)
8?Line Multiplexer
8?Input Priority Encoder
5?Bit Magnitude Comparator
Dual Binary to 1?4?Decoder (High)
|
ONSEMI[ON Semiconductor]
|
| NC7SZ175P6 NC7SZ175P6X NC7SZ175 NC7SZ175L6X |
TinyLogic UHS D-Type Flip-Flop LVC/LCX/Z SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, DSO6
TinyLogic UHS D-Type Flip-Flop
TinyLogic UHS D-Type Flip-Flop
|
Fairchild Semiconductor, Corp.
FAIRCHILD[Fairchild Semiconductor]
|
| 74AUP2G80GD125 74AUP2G80GM125 |
Low-power dual D-type flip-flop; positive-edge trigger; Package: SOT996-2 (XSON8U); Container: Reel Pack, Reverse, Reverse AUP/ULP/V SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO8
Low-power dual D-type flip-flop; positive-edge trigger; Package: SOT902-1 (XQFN8U); Container: Reel Pack, Reverse, Reverse
|
NXP Semiconductors N.V.
|
| MC100ELT23 MC100EL12DTR2 MC10H131FNR2 MC100H640FNR |
5V Dual Differential PECL to TTL Translator
5V ECL Low Impedance Driver
Dual Type D Master-Slave Flip-Flop
ECL/TTL Clock Driver
3.3V / 5V ECL Quad D Flip Flop with Set, Reset, and Differential Clock
3.3V / 5V ECL ÷4 Divider
Quad 2-Input NOR Gate
3.3V ECL Dual Differential Data and Clock D-Type Flip-Flop with Set and Reset
3.3V / 5V Hex Differential Line Receiver / Driver
3.3V / 5V Triple ECL Input to LVPECL/PECL Output Translator
|
ON Semiconductor
|
