| PART |
Description |
Maker |
| TB502-02 |
Layout Recommendation and Test Board for PLL502-02
|
PLL[PhaseLink Corporation]
|
| TB502-3X-520-XX |
Test Board for chip evaluation and Layout recommendations
|
PLL[PhaseLink Corporation]
|
| AAF0X |
Soldering Process Recommendation Guide
|
Tyco Electronics
|
| 0040.1012 0040.1013 0040.1015 0040.1011 0040.1014 |
TEST JACKS, TEST PROBES / PRUFSTECKER, PRUFBUCHSEN
|
Schurter Inc.
|
| LSSHS-5-04 |
Recommended P.C.B.Layout
|
Major League Electronics
|
| AN04-006 |
PWB Layout Considerations
|
Lineage Power Corporation
|
| AN576 |
PCB LAYOUT OPTIMISATION
|
SGS Thomson Microelectronics
|
| QFP44 |
POD Target Layout
|
iSYSTEM
|
| RM9W4S-50-ZB |
D-SUB HOUSING MIXED LAYOUT (9W4S)
|
Winchester Electronics ...
|
| RM9W4S-50-TB |
D-SUB HOUSING MIXED LAYOUT (9W4S)
|
Winchester Electronics ...
|
| LGA-8B01 |
Reference Pattern Layout Dimensions
|
Torex Semiconductor
|
