| PART |
Description |
Maker |
| BUL63A |
ADVANCED DISTRIBUTED BASE DESIGN
|
Seme LAB
|
| BUL65A |
ADVANCED DISTRIBUTED BASE DESIGN
|
Seme LAB
|
| BUL58B |
ADVANCED DISTRIBUTED BASE DESIGN HIGH VOLTAGE HIGH SPEED NPN SILICON POWER TRANSISTOR
|
SEME-LAB[Seme LAB]
|
| BUL56B BUL55B |
ADVANCED DISTRIBUTED BASE DESIGN HIGH VOLTAGE HIGH SPEED NPN SILICON POWER TRANSISTOR
|
SEME-LAB[Seme LAB]
|
| BUL52AFI |
ADVANCED DISTRIBUTED BASE DESIGN HIGH VOLTAGE HIGH SPEED NPN SILICON POWER TRANSISTOR
|
SemeLAB
SEME-LAB[Seme LAB]
|
| BUL50A |
ADVANCED DISTRIBUTED BASE DESIGN HIGH VOLTAGE HIGH SPEED NPN SILICON POWER TRANSISTOR
|
Seme LAB
TT electronics Semelab Limited
|
| BUL64B |
ADVANCED DISTRIBUTED BASE DESIGN HIGH VOLTAGE HIGH SPEED NPN SILICON POWER TRANSISTOR
|
SEME-LAB[Seme LAB]
SemeLAB
|
| BUL63B |
ADVANCED DISTRIBUTED BASE DESIGN HIGH VOLTAGE HIGH SPEED NPN SILICON POWER TRANSISTOR
|
SEME-LAB[Seme LAB]
SemeLAB
|
| AT40K-FFT AT40K05LV AT40K20 AT40K20LV AT40K40 AT40 |
AT40K-FFT [Updated 8/98. 8 Pages] Fast fourier transform Intellectual Property Core for AT40K FPGAs
From old datasheet system
5K - 50K Gate FPGA with DSP Optimized Core Cell and Distributed FreeRam.
20K Gate FPGA with DSP Optimized Core Cell and Distributed FreeRam (5V)
20K Gate FPGA with DSP Optimized Core Cell and Distributed FreeRam (3.3V)
40K Gate FPGA with DSP Optimized Core Cell and Distributed FreeRam (5V)
10K Gate FPGA with DSP Optimized Core Cell and Distributed FreeRam (5V)
10K Gate FPGA with DSP Optimized Core Cell and Distributed FreeRam (3.3V)
5K - 50K Gate FPGA with DSP Optimized Core Cell and Distributed FreeRam (3.3V)
5K Gate FPGA with DSP Optimized Core Cell and Distributed FreeRam (5V)
|
Atmel Corp
|
| DS1300-3 |
AC-DC / Distributed Power Front-End 2U
1300 Watts 12V Distributed Power System
|
ASTEC[Astec America, Inc]
Emerson Network Power
|
| DS450DC-309 DS450DC-3-002 DS550DC-3-003 DS450DC-3 |
AC-DC / Distributed Power Front-End 1U
450 - 550 Watts Distributed Power System
|
Emerson Network Power
|
| IT8673F |
Advanced Input / Output (Advanced I/O) Preliminary Specification V0.5
|
N.A.
ETC
|
