| PART |
Description |
Maker |
| ISPLSI2096VE-100LT128 ISPLSI2096VE-135LT128 ISPLSI |
3.3V In-System Programmable SuperFAST?/a> High Density PLD
CRYSTAL 24.0 MHZ 20PF SMD
3.3V In-System Programmable SuperFASTHigh Density PLD
3.3V In-System Programmable SuperFAST High Density PLD
3.3V In-System Programmable SuperFAST⑩ High Density PLD
3.3VIn-SystemProgrammableSuperFASTHighDensityPLD
|
Lattice Semiconductor Corporation
LATTICE[Lattice Semiconductor]
|
| CBRLDSH2-40 CBRLDSH2-40-15 |
SURFACE MOUNT HIGH DENSITY HIGH DENSITY SCHOTTKY BRIDGE RECTIFIER
|
Central Semiconductor C...
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| ISPLSI2032VE ISPLSI2032VE-110LB49 ISPLSI2032VE-110 |
225 MHz 3.3V in-system prommable superFAST high density PLD
3.3V In-System Programmable High Density SuperFAST?/a> PLD
3.3V In-System Programmable High Density SuperFAST?/a> PLD
3.3V In-System Programmable High Density SuperFAST⑩ PLD
3.3V In-System Programmable High Density SuperFAST PLD
IC,Normally-Open Panel-Mount Solid-State Relay,1-CHANNEL,M:HL048HD4.4
IC,Normally-Open Panel-Mount Solid-State Relay,1-CHANNEL,M:HL048HD4.3
IC,Normally-Closed Panel-Mount Solid-State Relay,1-CHANNEL,M:HL048HD4.4 EE PLD, 13 ns, PQCC44
3.3V In-System Programmable High Density SuperFASTPLD EE PLD, 13 ns, PQFP44
3.3V In-System Programmable High Density SuperFASTPLD EE PLD, 6 ns, PQCC44
3.3V In-System Programmable High Density SuperFASTPLD 3.3在系统可编程高密度PLD的超快⑩
3.3VIn-SystemProgrammableHighDensitySuperFASTPLD
|
LATTICE[Lattice Semiconductor]
Lattice Semiconductor Corporation
Lattice Semiconductor, Corp.
|
| QL2009 QL2009-0PB256C QL2009-0PB256I QL2009-0PF144 |
3.3V and 5.0V pASIC 2 FPGA combining speed, density, low cost and flexibility.
3.3V and 5.0V pASIC? 2 FPGA Combining Speed Density Low Cost and Flexibility
3.3V and 5.0V pASICò 2 FPGA
3.3V and 5.0V pASIC? 2 FPGA Combining Speed, Density, Low Cost and Flexibility
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility
3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility(高速，高可用密度，低成本、可适应性强.3V.0V pASIC 2系列场可编程逻辑器件)
PT 6C 6#20 PIN RECP
PT 8C 8#20 PIN RECP
3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility 3.3V.0V帕希奇？ 2 FPGA的结合速度，密度，低成本和灵活
|
List of Unclassifed Manufacturers
ETC[ETC]
Electronic Theatre Controls, Inc.
QuickLogic Corp.
|
| WP06R WP06R12D05 WP06R12D12 WP06R12D15 WP06R12S05 |
High Density 5-6 Watt Wide Input Range DC/DC Converter
5-6 WATT HIGH DENSITY, WIDE INPUT RANGE DC/DC CONVERTER
5-6 WATT HIGH DENSITY/ WIDE INPUT RANGE DC/DC CONVERTER
RECTIFIER SCHOTTKY SINGLE 2A 40V 50A-Ifsm 0.55Vf 0.5A-IR PowerDI-123 3K/REEL
|
CANDD[C&D Technologies]
|
| HDRIGHTANGLE 781-M15-113R141 781-M15-113R001 781-M |
MALE-HIGH DENSITY
MALE-HIGH DENSITY-MACHINED CONTACTS-RIGHT ANGLE
|
List of Unclassifed Manufacturers
|
| ISPLSI2032VE06 ISPLSI2032VE300LB49 ISPLSI2032VE300 |
3.3V In-System Programmable High Density SuperFAST⑩ PLD
3.3V In-System Programmable High Density SuperFAST?/a> PLD
3.3V In-System Programmable High Density SuperFAST PLD
3.3V In-System Programmable High Density SuperFAST垄芒 PLD
3.3V In-System Programmable High Density SuperFAST?/a> PLD
3.3V In-System Programmable High Density SuperFAST?PLD
|
Lattice Semiconductor
|
| ISPLSI2128VL-100LB100 ISPLSI2128VL-100LB208 ISPLSI |
2.5V In-System Programmable SuperFAST⑩ High Density PLD
2.5V In-System Programmable SuperFAST High Density PLD
2.5VIn-SystemProgrammableSuperFASTHighDensityPLD
Linear Motion Control; Series:LCL; Track Resistance:5kohm; Resistance Tolerance:20%; Power Rating:3W; Operating Temperature Range:-30 C to C; Resistor Element Material:Conductive Plastic RoHS Compliant: Yes
Linear Motion Control; Series:LCP8; Track Resistance:10kohm; Resistance Tolerance: /-15%; Power Rating:0.2W; Operating Temperature Range:-30 C to 105 C; Resistor Element Material:Conductive Plastic RoHS Compliant: Yes EE PLD, 13 ns, PBGA208
Resistors, Variable sliding; Series:LCP15; Track Resistance:10kohm; Resistance Tolerance: /-10%; Power Rating:0.5W; Operating Temperature Range:-30 C to 105 C; Resistor Element Material:Conductive Plastic RoHS Compliant: Yes EE PLD, 13 ns, PBGA100
2.5V In-System Programmable SuperFASTHigh Density PLD EE PLD, 10 ns, PBGA100
2.5V In-System Programmable SuperFASTHigh Density PLD EE PLD, 8.5 ns, PBGA208
2.5V In-System Programmable SuperFASTHigh Density PLD EE PLD, 10 ns, PQFP176
2.5V In-System Programmable SuperFASTHigh Density PLD EE PLD, 8.5 ns, PQFP100
2.5V In-System Programmable SuperFASTHigh Density PLD EE PLD, 8.5 ns, PBGA100
|
LATTICE[Lattice Semiconductor]
LatticeSemiconductor
Lattice Semiconductor Corporation
Lattice Semiconductor, Corp.
|
| M38230G4-XXXFP M38230G4-XXXHP M38231G4-XXXHP M3823 |
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V
18-Mbit (512K x 36/1M x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 512Kb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: QDR-II , 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
|
Renesas Electronics Corporation.
Renesas Electronics, Corp.
|
| SDHD7.5K SDHP7.5K SDHP15K SDHD15K SDHN7.5K |
STANDARD RECOVERY HIGH VOLTAGE DOUBLER AND CENTER TAPS
High Density,High Voltage,Standard Recovery Doubler Rectifier(反向电压7500V，温5℃时平均整流电流0.4A,高密高电标准恢复倍增整流
High Density,High Voltage,Standard Recovery Center Tap Rectifier(反向电压7500V，温5℃时平均整流电流0.8A,高密高电标准恢复正中心抽头整流器)
High Density,High Voltage,Standard Recovery Center Tap Rectifier(反向电压7500V，温25℃时平均整流电流0.8A,高密高电标准恢复正中心抽头整流器)
0.8 A, 7500 V, 2 ELEMENT, SILICON, SIGNAL DIODE
High Density,High Voltage,Standard Recovery Doubler Rectifier(反向电压15000V，温25℃时平均整流电流0.4A,高密高电标准恢复倍增整流 高密度，高电压，标准恢复倍流整流（反向电5000V，温25℃时平均整流电流0.4A，高密度，高电压，标准恢复倍增整流器）
|
Semtech Corporation
Semtech, Corp.
|
| CY14B104NA-ZSP20XCT CY14B104NA-ZSP20XIT CY14B104LA |
4 Mbit (512K x 8/256K x 16) nvSRAM; Organization: 256Kb x 16; Vcc (V): 2.7 to 3.6 V; Density: 4 Mb; Package: TSOP 256K X 16 NON-VOLATILE SRAM, 20 ns, PDSO54
4 Mbit (512K x 8/256K x 16) nvSRAM; Organization: 512Kb x 8; Vcc (V): 2.7 to 3.6 V; Density: 4 Mb; Package: FBGA
4 Mbit (512K x 8/256K x 16) nvSRAM; Organization: 256Kb x 16; Vcc (V): 2.7 to 3.6 V; Density: 4 Mb; Package: FBGA
|
Cypress Semiconductor, Corp.
CYPRESS SEMICONDUCTOR CORP
|
| ISPLSI5256VE-125LT100I ISPLSI5256VE-100LF256I ISPL |
In-system programmable 3.3V SuperWIDE high density PLD. fmax 80 MHz, tpd 12 ns.
EE PLD, 10 ns, PBGA256
In-system programmable 3.3V SuperWIDE high density PLD. fmax 100 MHz, tpd 10 ns.
In-system programmable 3.3V SuperWIDE high density PLD. fmax 125 MHz, tpd 7.5 ns.
In-system programmable 3.3V SuperWIDE high density PLD. fmax 165 MHz, tpd 6.0 ns.
|
Lattice Semiconductor, Corp.
LATTICE SEMICONDUCTOR CORP
|
|
