| PART |
Description |
Maker |
| 74LCX74SJ 74LCX74MX_NL 74LCX74 74LCX74BQX 74LCX74M |
Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs
Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, QCC14
|
FAIRCHILD[Fairchild Semiconductor]
Fairchild Semiconductor, Corp.
|
| HCTS374T HCTS374KTR HCTS374DTR |
Dual Positive-Edge-Triggered D-type Flip-Flops With Clear And Preset 20-LCCC -55 to 125
1024 x 18 Synchronous FIFO Memory 68-CPGA -55 to 125
Radiation Hardened Octal D-Type Flip-Flop, Three-State, Positive Edge Triggered
|
Intersil Corporation
|
| 74F109_00 74F109 74F109PC 74F109SC 74F109SJ 74F109 |
From old datasheet system
Dual JK Positive Edge-Triggered Flip-Flop
Dual JK# Positive Edge-Triggered Flip-Flop
|
FAIRCHILD[Fairchild Semiconductor]
|
| M27W201-80K6TR M27W201-200NZ6TR M27W201-80NZ6TR M2 |
2 MBIT (256KB X8) LOW VOLTAGE OTP EPROM
Test Spring Probe; Current Rating:3A; Leaded Process Compatible:Yes; Length:0.060"; Peak Reflow Compatible (260 C):No; Tip/Nozzle Style:90 Concave RoHS Compliant: Yes 2兆位56Kb × 8低压紫外线可擦写可编程只读存储器和OTP存储
Triple 3-Input Positive-AND Gates 14-SO 0 to 70
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-SO 0 to 70
Triple 3-Input Positive-AND Gates 14-PDIP 0 to 70
Triple 3-Input Positive-AND Gates 14-SOIC 0 to 70
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-SOIC 0 to 70
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-PDIP 0 to 70
2 Mbit 256Kb x 8 Low Voltage UV EPROM and OTP EPROM
2 MBIT (256KB X8) LOW VOLTAGE OTP EPROM
|
STMicroelectronics N.V.
意法半导
STMICROELECTRONICS[STMicroelectronics]
ST Microelectronics
|
| SN74LS109A-D |
Dual JK Positive Edge-Triggered Flip-Flop
|
ON Semiconductor
|
| KS74AHCT109 |
Dual J-K Positive Edge-Triggered Flip-Flops
|
Samsung
|
| DV74AC109 |
Dual JK Positive Edge-Triggered Flip-Flop
|
AVG Semiconductor
|
| DM7474 |
Dual Positive-Edge-Triggered D-Type Flip-Flops
|
Fairchild
|
| 74AUP2G80GD125 74AUP2G80GM125 |
Low-power dual D-type flip-flop; positive-edge trigger; Package: SOT996-2 (XSON8U); Container: Reel Pack, Reverse, Reverse AUP/ULP/V SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO8
Low-power dual D-type flip-flop; positive-edge trigger; Package: SOT902-1 (XQFN8U); Container: Reel Pack, Reverse, Reverse
|
NXP Semiconductors N.V.
|
| 74F50728 N74F50728N I74F50728D I74F50728N N74F5072 |
Synchronizing cascaded dual positive edge-triggered D-type flip-flop
|
NXP Semiconductors N.V.
PHILIPS[Philips Semiconductors]
|
| DM74LS109A DM74LS109AN DM74LS109 DM74LS109AM |
Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs
|
FAIRCHILD[Fairchild Semiconductor]
|
