| PART |
Description |
Maker |
| MAX3873AEGP |
16-Channel LVDM Transceiver 64-TSSOP -40 to 85
Low-Power, Compact 2.5Gbps/2.7Gbps Clock-Recovery and Data-Retiming IC
Low-Power / Compact 2.5Gbps/2.7Gbps Clock-Recovery and Data-Retiming IC
|
Maxim Integrated Products, Inc.
MAXIM - Dallas Semiconductor
|
| MAX3876 MAX3876EHJ MAX3876E_D MAX3876E/D |
2.5Gbps, Low-Power, #.3V Clock Recovery and Data Retiming IC
2.5Gbps, Low-Power, 3.3V Clock Recovery and Data Retiming IC
2.5Gbps / Low-Power / #.3V Clock Recovery and Data Retiming IC
|
MAXIM - Dallas Semiconductor
MAXIM[Maxim Integrated Products]
Maxim Integrated Products, Inc.
|
| MAX3875A MAX3875AEHJ MAX3875AE_D MAX3875AE/D |
"2.5Gbps, Low-Power, 3.3V Clock Recovery and Data Retiming IC"
From old datasheet system
|
Maxim Integrated Products
|
| MAX3873 |
Low-Power, Compact 2.5Gbps/2.7Gbps Clock-Recovery and Data-Retiming IC
From old datasheet system
|
MAXIM - Dallas Semiconductor
|
| NB6HQ14MMNHTBG NB6HQ14MMNG NB6HQ14MMNTXG |
2.5V 5GHz / 6.5Gbps Differential Input to 1.8V / 2.5V 1:4 CML Clock / Data Fanout Buffer
2.5V 5GHz / 6.5Gbps Differential Input to 1.8V / 2.5V 1:4 CML Clock / Data Fanout Buffer
|
ON Semiconductor
|
| PI2EQX4401ZFE PI2EQX4401 |
2.5Gbps x1 Lane Serial PCI Express Repeater/Equalizer with Clock Buffer
|
PERICOM[Pericom Semiconductor Corporation]
|
| W9725G6JB25I |
Double Data Rate architecture: two data transfers per clock cycle
|
Winbond
|
| M13S2561616A-2A |
Double-data-rate architecture, two data transfers per clock cycle
|
Elite Semiconductor Mem...
|
| SH713609 SH7137 |
SCI Clock Synchronous Simultaneous Transmit and Receive of Serial Data and DTC Data Transfer
|
Renesas Electronics Corporation
|
| MAX9320A MAX9320 MAX9320EUAT |
1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
1:2 Differential LVPECL/ LVECL/HSTL Clock and Data Drivers
|
Maxim Integrated Products, Inc.
MAXIM - Dallas Semiconductor
|
| NB6L11 NB6L11DTR2 NB6L11D NB6L11DR2 NB6L11DT |
2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL 1:2 CLOCK OR DATA FANOUT BUFFER / TRANSLATOR 6L SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
6GHz 2.5V/3.3V Multilevel Input to Differential LVNECL/LVPECL 1:2 Clock or Data Fanout Buffer/Transl
From old datasheet system
|
ONSEMI[ON Semiconductor]
|
