| PART |
Description |
Maker |
| CY37512P256-100BGI CY37064VP44-100AC CY37256 |
5V, 3.3V, ISR High-Performance CPLDs
|
Cypress Semiconductor, Corp.
|
| CY37064VP48-100BAC CY37512 CY37000 CY37032 CY37064 |
5V, 3.3V, ISR High-Performance CPLDs
From old datasheet system
COMPLEX-EEPLD,64-CELL,12NS PROP DELAY,BGA,48PIN,PLASTIC
|
CYPRESS[Cypress Semiconductor]
Cypress Semiconductor Corp
|
| CY3600I |
Programmable Logic 可编程逻辑
FLASH370i ISR Programming Kit
|
Electronic Theatre Controls, Inc.
Cypress Semiconductor
|
| A29L160AUG-90IF A29L160ATG-70IF A29L160ATV-90IF A2 |
Replaced by PT78NR112,PT78ST112 : 12Vout 1.5A Wide Input Positive Step-Down ISR 3-SIP MODULE -40 to 85 2米x 8 1米16位CMOS 3.3伏只，引导扇区闪
Replaced by PT78ST114,PT78NR114 : 13.9Vout 1.5A Wide Input Positive Step-Down ISR 3-SIP MODULE -40 to 85 2米x 8 1米16位CMOS 3.3伏只，引导扇区闪
2M X 8 Bit / 1M X 16 Bit CMOS 3.3 Volt-only, Boot Sector Flash Memory 2米x 8 1米16位CMOS 3.3伏只，引导扇区闪
Replaced by PT78NR115,PT78ST115 : 15V 1.5A Wide-Input Positive Step-Down ISR 3-SIP MODULE -40 to 85 2米x 8 1米16位CMOS 3.3伏只，引导扇区闪
ER 47C 7#12 40#16 PIN RECP
Circular Connector; No. of Contacts:16; Series:; Body Material:Aluminum Alloy; Connecting Termination:Solder; Connector Shell Size:36; Circular Contact Gender:Socket; Circular Shell Style:Box Mount Receptacle RoHS Compliant: No
Replaced by PT78NR152,PT78ST153 : 5.25Vout 1.5A Wide Input Positive Step-Down ISR 3-SIP MODULE -40 to 85
Replaced by PT78ST110,PT78NR110 : 10Vout 1.5A Wide Input Positive Step-Down ISR 3-SIP MODULE -40 to 85
ER 19C 19#16 SKT RECP BOX
ER 8C 8#12 PIN RECP
ER 60C 60#16 SKT RECP BOX
Circular Connector; No. of Contacts:31; Series:; Body Material:Aluminum Alloy; Connecting Termination:Solder; Connector Shell Size:36; Circular Contact Gender:Socket; Circular Shell Style:Box Mount Receptacle RoHS Compliant: No
|
http://
AMIC Technology, Corp.
AMIC Technology Corporation
|
| M38030F2L-XXXHP M38030F2L-XXXKP M38030F2L-XXXSP M3 |
256 Kbit (32K x 8) nvSRAM; Organization: 32Kb x 8; Vcc (V): 2.7 to 3.6 V; Density: 256 Kb; Package: SOIC
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 5; Operating Range: 0 to 70 C
256K (32K x 8) Static RAM; Density: 256 Kb; Organization: 32Kb x 8; Vcc (V): 4.50 to 5.50 V;
Three-PLL General Purpose FLASH Programmable Clock Generator; Voltage (V): 3.3 V; Input Range: 1 MHz to 166 MHz; Output Range: 1 MHz to 200 MHz; Outputs: 6
5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 256; Vcc (V): 3.3; fMax (MHz): 66; tPD (ns): 12
8-Mbit (512K x 16) Static RAM; Density: 8 Mb; Organization: 512Kb x 16; Vcc (V): 2.20 to 3.60 V;
9-Mbit (256K x 36/512K x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 9 Mb; Organization: 512Kb x 18; Vcc (V): 3.1 to 3.6 V
9-Mbit (256K x 36/512K x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 9 Mb; Organization: 512Kb x 18; Vcc (V): 3.1 to 3.6 V
18-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 1.7 to 1.9 V
Four Output PCI-X and General Purpose Buffer; Voltage (V): 3.3 V; Frequency Range: 0 MHz to 140 MHz; Outputs: 4; Operating Range: 0 to 70 C
18-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 1.7 to 1.9 V
9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 9 Mb; Organization: 512Kb x 18; Vcc (V): 3.1 to 3.6 V
9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 9 Mb; Organization: 512Kb x 18; Vcc (V): 2.4 to 2.6 V
4-Mbit (512K x 8) Static RAM; Density: 4 Mb; Organization: 512Kb x 8; Vcc (V): 4.50 to 5.50 V;
4-Mbit (256K x 16) Static RAM; Density: 4 Mb; Organization: 256Kb x 16; Vcc (V): 2.20 to 3.60 V;
64K x 16 Static RAM; Density: 1 Mb; Organization: 64Kb x 16; Vcc (V): 3.0 to 3.6 V;
1-Mbit (64K x 16) Static RAM; Density: 1 Mb; Organization: 64Kb x 16; Vcc (V): 4.5 to 5.5 V;
9-Mbit (256K x 36/512K x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 9 Mb; Organization: 256Kb x 36; Vcc (V): 3.1 to 3.6 V
1-Mbit (64K x 16) Static RAM; Density: 1 Mb; Organization: 64Kb x 16; Vcc (V): 3.0 to 3.6 V;
4 Mbit (512K x 8/256K x 16) nvSRAM; Organization: 512Kb x 8; Vcc (V): 2.7 to 3.6 V; Density: 4 Mb; Package: TSOP
4 Mbit (512K x 8/256K x 16) nvSRAM; Organization: 256Kb x 16; Vcc (V): 2.7 to 3.6 V; Density: 4 Mb; Package: TSOP
16-Mbit (1M x 16 / 2M x 8) Static RAM; Density: 16 Mb; Organization: 1Mb x 16; Vcc (V): 4.50 to 5.50 V;
4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, BUSY; Density: 128 Kb; Organization: 8Kb x 16; Vcc (V): 4.5 to 5.5 V; Speed: 35 ns
9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 9 Mb; Organization: 256Kb x 36; Vcc (V): 3.1 to 3.6 V
9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 9 Mb; Organization: 256Kb x 36; Vcc (V): 3.1 to 3.6 V
9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 9 Mb; Organization: 256Kb x 36; Vcc (V): 2.4 to 2.6 V
9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 9 Mb; Organization: 512Kb x 18; Vcc (V): 3.1 to 3.6 V
8-Mbit (512K x 16) Static RAM; Density: 8 Mb; Organization: 512Kb x 16; Vcc (V): 4.50 to 5.50 V;
9-Mbit (256K x 36/512K x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 9 Mb; Organization: 256Kb x 36; Vcc (V): 3.1 to 3.6 V
256K x 16 Static RAM; Density: 4 Mb; Organization: 256Kb x 16; Vcc (V): 4.5 to 5.5 V;
9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM; Architecture: Standard Sync, Pipeline DCD; Density: 9 Mb; Organization: 256Kb x 36; Vcc (V): 3.1 to 3.6 V
4-Mbit (256K x 16) Static RAM; Density: 4 Mb; Organization: 256Kb x 16; Vcc (V): 3.0 to 3.6 V;
8-Mbit (1024K x 8) Static RAM; Density: 8 Mb; Organization: 1Mb x 8; Vcc (V): 2.20 to 3.60 V;
18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V
256K x 16 Static RAM; Density: 4 Mb; Organization: 256Kb x 16; Vcc (V): 3.0 to 3.6 V;
8-Mbit (1M x 8) Static RAM; Density: 8 Mb; Organization: 1Mb x 8; Vcc (V): 2.20 to 3.60 V;
3.3V Zero Delay Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 8; Operating Range: -40 to 85 C
Programmable Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating Range: -40 to 85 C
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V
18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
512K x 8 Static RAM; Density: 4 Mb; Organization: 512Kb x 8; Vcc (V): 4.5 to 5.5 V;
18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 2.4 to 2.6 V
2.5V or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 MHz to 200 MHz; Outputs: 12; Operating Range: -40 to 85 C
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 5; Operating Range: -40 to 85 C
2M x 8 Static RAM; Density: 16 Mb; Organization: 2Mb x 8; Vcc (V): 3.0 to 3.6 V;
16 Mbit (512K X 32) Static RAM; Density: 16 Mb; Organization: 512Kb x 32; Vcc (V): 3.0 to 3.6 V;
3.3V Zero Delay Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 8; Operating Range: 0 to 70 C
8-Mbit (1M x 8) Static RAM; Density: 8 Mb; Organization: 1Mb x 8; Vcc (V): 3.0 to 3.6 V;
5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 64; Vcc (V): 5; fMax (MHz): 125; tPD (ns): 6
2-Mbit (128K x 16) Static RAM; Density: 2 Mb; Organization: 128Kb x 16; Vcc (V): 3.0 to 3.6 V;
16-Mbit (1M x 16) Static RAM; Density: 16 Mb; Organization: 1Mb x 16; Vcc (V): 3.0 to 3.6 V;
4-Mbit (256K x 18) Pipelined DCD Sync SRAM; Architecture: Standard Sync, Pipeline DCD; Density: 4 Mb; Organization: 256Kb x 18; Vcc (V): 3.1 to 3.6 V
512K (32K x 16) Static RAM; Density: 512 Kb; Organization: 32Kb x 16; Vcc (V): 3.0 to 3.6 V;
4-Mbit (128K x 36) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 4 Mb; Organization: 128Kb x 36; Vcc (V): 3.1 to 3.6 V
1M x 16 Static RAM; Density: 16 Mb; Organization: 1Mb x 16; Vcc (V): 3.0 to 3.6 V;
Programmable Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating Range: 0 to 70 C
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 9; Operating Range: 0 to 70 C
MoBL(R) 2 Mbit (128K x 16) Static RAM; Density: 2 Mb; Organization: 128Kb x 16; Vcc (V): 2.20 to 3.60 V;
Rambus(R) XDR(TM) Clock Generator; VDD: 2.5 V; Input Frequency: 100 MHz to 133 MHz; Output Frequency: 300 MHz to 800 MHz; # Out: 4
2-Mbit (128K x 16) Static RAM; Density: 2 Mb; Organization: 128Kb x 16; Vcc (V): 2.20 to 3.60 V;
4-Mbit (128K x 36) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 4 Mb; Organization: 128Kb x 36; Vcc (V): 3.1 to 3.6 V
5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 128; Vcc (V): 5; fMax (MHz): 167; tPD (ns): 7
2.5V or 3.3V, 200-MHz, 1:10 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 MHz to 200 MHz; Outputs: 10; Operating Range: 0 to 70 C
5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 128; Vcc (V): 5; fMax (MHz): 100; tPD (ns): 7
5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 128; Vcc (V): 5; fMax (MHz): 125; tPD (ns): 7
18-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 1.7 to 1.9 V
Low Voltage Programmable Skew Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating Range: 0 to 70 C
Spread Spectrum Clock Generator; Voltage(V): 3.3 V; Input Frequency Range: 25 MHz to 100 MHz; Output Frequency Range: 25 MHz to 100 MHz; Operating Range: 0 to 70 C; Package: SOIC
Low Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating Range: 0 to 70 C
5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 64; Vcc (V): 3.3; fMax (MHz): 143; tPD (ns): 9 单芯位CMOS微机
5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 64; Vcc (V): 5; fMax (MHz): 154; tPD (ns): 6 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机
5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 64; Vcc (V): 3.3; fMax (MHz): 100; tPD (ns): 9 单芯位CMOS微机
5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 128; Vcc (V): 3.3; fMax (MHz): 83; tPD (ns): 10 单芯位CMOS微机
5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 64; Vcc (V): 5; fMax (MHz): 125; tPD (ns): 6 单芯位CMOS微机
Three-PLL General-Purpose EPROM Programmable Clock Generator; Voltage (V): 3.3/5.0 V; Input Range: 1 MHz to 30 MHz; Output Range: .077 MHz to 100 MHz; Outputs: 6 单芯位CMOS微机
8-Mbit (512K x 16) MoBL(R) Static RAM; Density: 8 Mb; Organization: 512Kb x 16; Vcc (V): 2.20 to 3.60 V; 单芯位CMOS微机
High Speed Low Voltage Programmable Skew Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 3.75 MHz to 110 MHz; Outputs: 8; Operating Range: 0 to 70 C 单芯位CMOS微机
3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs; Voltage (V): 3.3 V; Frequency Range: 0 MHz to 100 MHz; Outputs: 10; Operating Range: 0 to 70 C 单芯位CMOS微机
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 9; Operating Range: -40 to 85 C 单芯位CMOS微机
Programmable Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating Range: -40 to 85 C 单芯位CMOS微机
2-Mbit (128K x 16) Static RAM; Density: 2 Mb; Organization: 128Kb x 16; Vcc (V): 3.0 to 3.6 V; 单芯位CMOS微机
MoBL(R) 1 Mbit (128K x 8) Static RAM; Density: 1 Mb; Organization: 128Kb x 8; Vcc (V): 2.20 to 3.60 V; 单芯位CMOS微机
18-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
1-Mbit (128K x 8) Static RAM; Density: 1 Mb; Organization: 128Kb x 8; Vcc (V): 4.50 to 5.50 V; 单芯位CMOS微机
4-Mbit (256K x 18) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 4 Mb; Organization: 256Kb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
2-Mbit (64K x 32) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 2 Mb; Organization: 64Kb x 32; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
200-MHz Field Programmable Zero Delay Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 10 MHz to 200 MHz; Outputs: 12; Operating Range: -40 to 85 C 单芯位CMOS微机
2-Mbit (128K x 16) Static RAM; Density: 2 Mb; Organization: 128Kb x 16; Vcc (V): 2.20 to 3.60 V; 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机
2-Mbit (256K x 8) Static RAM; Density: 2 Mb; Organization: 256Kb x 8; Vcc (V): 2.20 to 3.60 V; 单芯8位CMOS微机
Very Low Jitter Field and Factory Programmable Clock Generator; Voltage (V): 3.3 V; Input Range: 10 MHz to 133 MHz; Output Range: 20 MHz to 200 MHz; Outputs: 2 单芯位CMOS微机
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 5; Operating Range: 0 to 70 C 单芯位CMOS微机
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 5; Operating Range: -40 to 85 C 单芯位CMOS微机
Three-PLL General Purpose FLASH Programmable Clock Generator; Voltage (V): 3.3 V; Input Range: 1 MHz to 166 MHz; Output Range: 0 MHz to 200 MHz; Outputs: 3 单芯位CMOS微机
1:8 Clock Fanout Buffer; Voltage (V): 3.3 V; Frequency Range: 0 MHz to 350 MHz; Outputs: 8; Operating Range: -40 to 85 C 单芯位CMOS微机
Quad PLL Clock Generator with 2-Wire Serial Interface; Voltage (V): 2.5/3.3 V; Input Range: 27 MHz to 27 MHz; Output Range: 4.2 MHz to 166 MHz; Outputs: 5 单芯位CMOS微机
2.5V or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 MHz to 200 MHz; Outputs: 12; Operating Range: 0 to 70 C 单芯位CMOS微机
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 9; Operating Range: 0 to 70 C 单芯位CMOS微机
High Speed Multi-phase PLL Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 24 MHz to 200 MHz; Outputs: 11; Operating Range: 0 to 70 C 单芯位CMOS微机
2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 MHz to 200 MHz; Outputs: 18; Operating Range: -40 to 85 C 单芯位CMOS微机
-bit AVR Microcontroller with 8K Bytes In- System Programmable Flash 位AVR微控制器具有8K字节的系统内可编程闪
2.5V or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 MHz to 200 MHz; Outputs: 12; Operating Range: 0 to 70 C
1:8 Clock Fanout Buffer; Voltage (V): 3.3 V; Frequency Range: 0 MHz to 350 MHz; Outputs: 8; Operating Range: 0 to 70 C
Spread Spectrum Clock Generator; Voltage(V): 3.3 V; Input Frequency Range: 4 MHz to 32 MHz; Output Frequency Range: 4 MHz to 32 MHz; Operating Range: 0 to 70 C; Package: SOIC
High Speed Low Voltage Programmable Skew Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 3.75 MHz to 110 MHz; Outputs: 8; Operating Range: 0 to 70 C
5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 64; Vcc (V): 3.3; fMax (MHz): 100; tPD (ns): 9
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Renesas Electronics Corporation.
Renesas Electronics, Corp.
|
| CY39100V388B-83MGC CY39100V208B-125NTXC CY39050V20 |
Delta39K™ ISR™ CPLDs at FPGA Densities™ LOADABLE PLD, 15 ns, PBGA388
Delta39K™ ISR™ CPLDs at FPGA Densities™ LOADABLE PLD, 10 ns, PQFP208
CPLDs at FPGA Densities LOADABLE PLD, 10 ns, PQFP208
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Cypress Semiconductor, Corp.
|
| SST34HF3223B-90-4C-LP SST34HF3223B-70-4C-LP SST34H |
KIT ISR PROGRAMMING NO WARP
One-PLL General-Purpose Flash-Programmable and 2-Wire Serially Programmable Clock Generator
混合存储器|静态存储器EEPROM中|CMOS | BGA封装| 56PIN |塑料
MIXED MEMORY|SRAM EEPROM|CMOS|BGA|56PIN|PLASTIC 混合存储器|静态存储器EEPROM中|的CMOS | BGA封装| 56PIN |塑料
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Silicon Storage Technology, Inc.
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| A29L400UG-90U A29L400UV-90U A29L400TM-90 A29L400TM |
512K X 8 Bit / 256K X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory 12k × 8 256 × 16位的CMOS 3.0伏只，引导扇区闪
240 x 128 pixel format, LED or EL Backlight
128 x 64 pixel format, LED Backlight available
Replaced by PT78ST109 : 9Vout 1.5A Wide Input Positive Step-Down ISR 3-SIP MODULE -40 to 85
CARRY CASE FOR 300 SERIES DMM
640 x 480 pixel format, CCFL Backlight
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http://
AMIC Technology, Corp.
AMIC Technology Corporation
|
| A29L800UG-90U A29L800UV-90U A29L800TM-90 A29L800TM |
240 x 128 pixel format, LED or EL Backlight 100万8 16位为512k ×电压的CMOS 3.0只，引导扇区闪存
1M X 8 Bit / 512K X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory 100万8 16位为512k ×电压的CMOS 3.0只，引导扇区闪存
128 x 64 pixel format, LED Backlight available
Replaced by PT78ST133 : 3.3Vout 1.5A Wide Input Positive Step-Down ISR 3-SIP MODULE -40 to 85
Function Generator Carrying Case RoHS Compliant: NA
640 x 480 pixel format, CCFL Backlight
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http://
AMIC Technology, Corp.
AMIC Technology Corporation
|
| ATF22V10 ATF22V10B ATF22V10B-10JC ATF22V10B-10JI A |
High- Performance EE PLD FLASH PLD, 25 ns, PDSO24
High- Performance EE PLD FLASH PLD, 25 ns, PDIP24
Single Supply, Dual SPST Switch FLASH PLD, 15 ns, PDIP24
High- Performance EE PLD FLASH PLD, 15 ns, PDIP24
High- Performance EE PLD FLASH PLD, 15 ns, PDSO24
High- Performance EE PLD FLASH PLD, 10 ns, PDIP24
High- Performance EE PLD FLASH PLD, 15 ns, PQCC28
High- Performance EE PLD FLASH PLD, 10 ns, CQCC28
High- Performance EE PLD FLASH PLD, 15 ns, CDIP24
High- Performance EE PLD FLASH PLD, 7.5 ns, PDIP24
High- Performance EE PLD FLASH PLD, 7.5 ns, PDSO24
High- Performance EE PLD FLASH PLD, 10 ns, PDSO24
3.3V, 1 Output, LVTTL to LVPECL Clock Converter
CAP 470PF 16V 5% X7R SMD-0603 TR-7 PLATED-NI/SN
High-performance EE PLD
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Atmel, Corp.
Atmel Corp.
ATMEL[ATMEL Corporation]
http://
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| SB3H100-E3_54 SB3H100-E3_73 SB3H90 SB3H9008 SB3H10 |
High-Voltage Schottky Rectifier High Barrier Technology for Improved High Temperature Performance
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Vishay Siliconix
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