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Part No. |
MT8VDDT1664AG-403A1
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OCR Text |
...d = +2.3v to +3.6v 2.5v i/o (sstl_2 compatible) commands entered on each positive ck edge dqs edge-aligned with data for reads; center- aligned with data for writes internal, pipelined double data rate (ddr) architec- ture; two dat... |
Description |
16M X 64 DDR DRAM MODULE, 0.6 ns, DMA184
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File Size |
335.96K /
16 Page |
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it Online |
Download Datasheet
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NANYA TECHNOLOGY CORP
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Part No. |
NT5DS64M8AF-6K
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OCR Text |
...riodic refresh interval 2.5v (sstl_2 compatible) i/o v ddq = 2.5v 0.2v v dd = 2.5v 0.2v 6k speed sort: supports pc2700/pc2100 modules 75b speed sort: supports pc2100 modules description the 512mb ddr sdram is a high-speed c... |
Description |
64M X 8 DDR DRAM, 0.7 ns, PBGA60
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File Size |
2,293.16K /
76 Page |
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it Online |
Download Datasheet
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Part No. |
MT8VDDT1664AG-202A1
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OCR Text |
...v dd q = +2.5v 0.2v 2.5v i/o (sstl_2 compatible) commands entered on each positive ck edge dqs edge-aligned with data for reads; center- aligned with data for writes internal, pipelined double data rate (ddr) architecture; two data ... |
Description |
16M X 64 DDR DRAM MODULE, 0.8 ns, DMA184
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File Size |
403.49K /
23 Page |
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it Online |
Download Datasheet
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Price and Availability
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