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differential lvcmos-to-0.7v Datasheet PDF File

For differential lvcmos-to-0.7v Found Datasheets File :: 569 Search Time::3.25ms
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				ICST[Integrated Circuit Systems]
Part No.	ICS843023 ICS843023AG ICS843023AGT
OCR Text	... CLOCK GENERATOR FEATURES * 1 differential 3.3V LVPECL output * Crystal oscillator interface designed for 25MHz, 18pF parallel resonant cr...LVCMOS/LVTTL interface levels. differential clock outputs. LVPECL interface levels. TABLE 1. PIN ...
Description	3.3V, 250MHZ LVPECL CLOCK GENERATOR
File Size	167.19K / 10 Page	View it Online	Download Datasheet

				PHOENIX CONTACT Deutschland GmbH ICST[Integrated Circuit Systems]
Part No.	ICS843031 ICS843031AG ICS843031AGT
OCR Text	... CLOCK GENERATOR FEATURES * 1 differential 3.3V LVPECL output * Crystal oscillator interface designed for 18pF parallel resonant crystals ...LVCMOS/LVTTL interface levels. differential clock outputs. LVPECL interface levels. TABLE 1. PIN ...
Description	CABLE ASSEMBLY; BANANA PLUG TO BANANA PLUG; 50 OHM, RG316/U COAX; 72" CABLE LENGTH FEMTOCLOCKS⑩晶体至3.3V的LVPECL时钟发生 FEMTOCLOCKS⑩ CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR FEMTOCLOCKS CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
File Size	200.89K / 11 Page	View it Online	Download Datasheet

				Integrated Circuit Syst... ICST[Integrated Circuit Systems] NXP Semiconductors N.V. DOMINANT Opto Technologies Sdn. Bhd.
Part No.	ICSSSTV16857 ICSSSTV16857YL-T ICS16857 ICSSSTV16857YG-T ICSSSTV16857YGLF-T
OCR Text	...ory Modules Product Features: * differential clock signal * Meets SSTL_2 signal data * Supports SSTL_2 class I & II specifications * low-vol...LVCMOS. Data flow from D to Q is controlled by the differential clock, CLK, CLK# and RESET#. Data is...
Description	SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48 0.240 INCH, 0.50 MM PITCH, TSSOP-48 DDR 14-Bit Registered Buffer 复员14位注册缓冲区
File Size	112.85K / 8 Page	View it Online	Download Datasheet

				ICST[Integrated Circuit Systems]
Part No.	ICSSSTV16859 ICSSSTV16859YK
OCR Text	...ory Modules Product Features: * differential clock signals * Meets SSTL_2 signal data * Supports SSTL_2 class II specifications on outputs *...LVCMOS. Data flow from D to Q is controlled by the differential clock, CLK, CLK# and RESET#. Data is...
Description	DDR 13-Bit to 26-Bit Registered Buffer
File Size	231.88K / 8 Page	View it Online	Download Datasheet

				IDT[Integrated Device Technology] Integrated Device Technology, Inc.
Part No.	IDT74SSTV16857 IDT74SSTV16857PA IDT74SSTV16857PAG IDT74SSTV16857PAG8 IDT74SSTV16857PA8
OCR Text	...ss II style data inputs/outputs differential CLK input RESET control compatible with LVCMOS levels Flow-through architecture for optimum PCB design Drive up to equivalent of 14 SDRAM loads Latch-up performance exceeds 100mA ESD >2000V per M...
Description	14-BIT REGISTERED BUFFER WITH SSTL I/O
File Size	52.38K / 6 Page	View it Online	Download Datasheet

				MAXIM - Dallas Semiconductor MAXIM[Maxim Integrated Products]
Part No.	MAX9115 MAX9115EXK-T
OCR Text	differential signaling (LVDS) line receiver ideal for applications requiring high data rates, low power, and low noise. The device is guaran...LVCMOS output. The fail-safe feature sets the output high when the inputs are undriven and open, ter...
Description	Single LVDS Line Receiver in SC70
File Size	136.50K / 8 Page	View it Online	Download Datasheet

				Fairchild Semiconductor
Part No.	SSTV16857 SSTV16857MTD
OCR Text	...emory modules. The device has a differential input clock, SSTL-2 compatible data inputs and a LVCMOS compatible RESET input. The device has been designed for compliance with the JEDEC DDR module and register specifications. The device is fa...
Description	From old datasheet system 14-Bit Register with SSTL-2 Compatible I/O and Reset
File Size	75.80K / 6 Page	View it Online	Download Datasheet

For differential lvcmos-to-0.7v Found Datasheets File :: 569 Search Time::3.25ms
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