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Samsung Electronic
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| Part No. |
STD110ASIC
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| OCR Text |
...gic simulation: cadence verilog-xl, cadence nc-verilog, viewlogic viewsim, mentor modelsim-vhdl, mentor modelsim-verilog, synopsys vss, syno...density, but reduced accuracy for analog components and reduced signal range (reduced dynamic range)... |
| Description |
PLL 2013X
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| File Size |
140.12K /
50 Page |
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Altera Corporation
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| Part No. |
EPF10K50RC240 EPF10K10LC84-4 EPF10K20TI144-4 EPF10K100A EPF10K130V EPF10K20 EPF10K30 EPF10K40 EPF10K50 EPF10K70
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| OCR Text |
...h tools such as Cadence Verilog-XL. Additionally, the Altera software contains EDA libraries that use devicespecific features such as carry chains which are used for fast counter and arithmetic functions. For instance, the Synopsys Design C... |
| Description |
Embedded Programmable Logic Device Family
IC,FPGA,1152-CELL,CMOS,QFP,144PIN,PLASTIC
IC,FPGA,576-CELL,CMOS,LDCC,84PIN,PLASTIC
IC,FPGA,360-CELL,CMOS,QFP,240PIN,PLASTIC
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| File Size |
651.07K /
128 Page |
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it Online |
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XILINX
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| Part No. |
XC9500XL
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| OCR Text |
...with the Xilinx Virtex, Spartan-XL and XC4000XL FPGA families, allowing system designers to partition logic optimally between fast interface circuitry and high-density general purpose logic. As shown in Table 1, logic density of the XC9500X... |
| Description |
XC9500XL High-Performance CPLD Family
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| File Size |
136.53K /
17 Page |
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it Online |
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Xilinx
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| Part No. |
XC9500XV DS049
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| OCR Text |
...closely with the Xilinx Spartan-XL and Virtex FPGA families, allowing system designers to partition logic optimally between fast interface circuitry and high-density general purpose logic. As shown in Table 1, logic density of the XC9500XV ... |
| Description |
Advance Product Specification
From old datasheet system
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| File Size |
167.22K /
18 Page |
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Honeywell International, Inc.
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| Part No. |
CE61F30
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| OCR Text |
...a support verifire vcs, verilog-xl, (vcs, cadence tools, sign-off simulation, veritime, synopsys, synthesis) verifault, design compiler (synopsys) vhdlfire all vital compliance tools, sign-off simulation, design time, design compiler othe... |
| Description |
FPGA FPGA
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| File Size |
153.31K /
2 Page |
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it Online |
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Price and Availability
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