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sleep-mode Datasheet PDF File

For sleep-mode Found Datasheets File :: 16115 Search Time::1.875ms
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				SONY[Sony Corporation]
Part No.	CXP973F064
OCR Text	...ort. This LSI also provides the sleep/stop functions that enable lower power consumption. 100 pin QFP (Plastic) 100 pin LQFP (Plastic) 10...mode) -- Timers 8-bit timer/counter, 2 channels (with timing output) 16-bit capture timer/counter (w...
Description	CMOS 16-bit Single Chip Microcomputer CMOS 16-bit Single Chip Microcomputer
File Size	446.38K / 42 Page	View it Online	Download Datasheet

				Cypress Semiconductor, Corp. Cypress Semiconductor Corp. CYPRESS[Cypress Semiconductor]
Part No.	CY7C1351F CY7C1351F-100AC CY7C1351F-100AI CY7C1351F-100BGC CY7C1351F-100BGI CY7C1351F-117AC CY7C1351F-117AI CY7C1351F-117BGC CY7C1351F-117BGI CY7C1351F-133AC CY7C1351F-133AI CY7C1351F-133BGC CY7C1351F-133BGI CY7C1351F-66AC CY7C1351F-66AI CY7C1351F-66BGC CY7C1351F-66BGI CY7C1351
OCR Text	...NPUT REGISTER READLOGIC E SLEEP Control 1 Note: 1. For best-practices recommendations, please refer to the Cypress application n...MODE NC A A A A A A A Document #: 38-05210 Rev. *B A A A A ...
Description	4-Mb (128K x 36) Flow-through SRAM with NoBLArchitecture 128K X 36 ZBT SRAM, 7.5 ns, PQFP100 4-Mb (128K x 36) Flow-through SRAM with NoBLArchitecture 128K X 36 ZBT SRAM, 11 ns, PBGA119 4-Mb (128K x 36) Flow-through SRAM with NoBLArchitecture 128K X 36 ZBT SRAM, 8 ns, PQFP100 4-Mb (128K x 36) Flow-through SRAM with NoBLArchitecture 128K X 36 ZBT SRAM, 8 ns, PBGA119 4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture 4-Mb (128K x 36) Flow-through SRAM with NoBL Architecture
File Size	423.97K / 15 Page	View it Online	Download Datasheet

				CYPRESS[Cypress Semiconductor]
Part No.	CY7C1484V33 CY7C1484V33-167AC CY7C1484V33-167BGC CY7C1484V33-167BZC CY7C1484V33-200AC CY7C1484V33-200BGC CY7C1484V33-200BZC CY7C1484V33-250AC CY7C1484V33-250BGC CY7C1484V33-250BZC CY7C1485V33 CY7C1485V33-167AC CY7C1485V33-167BGC CY7C1485V33-167BZC CY7C1485V33-200AC CY7C1485V33-200BGC CY7C1485V33-200BZC CY7C1485V33-250AC CY7C1485V33-250BGC CY7C1485V33-250BZC
OCR Text	...D ENABLE DELAY Q REGISTER OE ZZ SLEEP CONTROL OUTPUT REGISTERS CLK INPUT REGISTERS CLK DQa,b,c,d DPa,b,c,d CY7C1485V33-4M x 18 MODE (A[1;0]) 2 CLK ADV ADSC ADSP A[21:0] GW BWE BW b BWa BURST Q0 CE COUNTER Q1 CLR Q 22 20 D ADDRE...
Description	2M x 36/4M x 18 Pipelined DCD SRAM
File Size	505.55K / 29 Page	View it Online	Download Datasheet

				EMC[ELAN Microelectronics Corp]
Part No.	EM78811
OCR Text	...es (internal clock 3.679MHz) 1. sleep mode : CPU and 3.679MHz clock turn off, 32.768KHz clock turn off 2. Idle mode : CPU and 3.679 MHz clock turn off, 32.768KHz clock turn on 3. Green mode : 3.679MHz clock turn off, CPU and 32.768KHz clock...
Description	8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
File Size	162.49K / 33 Page	View it Online	Download Datasheet

				ELAN Microelectronics Corp
Part No.	EM78P156EL EM78P156ELAS EM78P156ELKM EM78P156ELM EM78P156ELP
OCR Text	...3V/32KHz * Typically 1 A during sleep mode * 1K x 13 bits on chip ROM * One security register to prevent intrusion of OTP memory codes * One configuration register to accommodate user's requirements * 48x 8 bits on chip registers (SRAM, gen...
Description	8-bit microprocessor designed and developed with low-power and high-speed CMOS technology
File Size	578.39K / 39 Page	View it Online	Download Datasheet

				义隆 EMC [ELAN Microelectronics Corp]
Part No.	EM78P156E EM78P156E.PDF
OCR Text	...KHz * typical of 1 A during the sleep mode 1Kx13 bits on chip ROM One security register to prevent the code in the OTP memory from intruding One configuration register to match the user's requirements 48x8 bits on chip registers (SRAM) 2 bi...
Description	From old datasheet system 8 Bit MCU 8-bit microprocessor with low-power and high-speed CMOS technology
File Size	141.64K / 28 Page	View it Online	Download Datasheet

				ELAN Microelectronics Corp
Part No.	EM78P447 EM78P447S EM78P447SA EM78P447SB
OCR Text	...2KHz * typical of 1A during the sleep mode 4096 x 13 bits on chip ROM 148 x 8 bits on chip registers (SRAM) 3 bi-directional I/O ports 5 level stacks for subroutine and interrupt 8-bit real time clock/counter (TCC) with selective signal sou...
Description	8-bit microprocessor with low-power and high-speed CMOS technology
File Size	132.78K / 27 Page	View it Online	Download Datasheet

				ELAN Microelectronics Corp EMC
Part No.	EM78P458 EM78P459 EM78P458AM EM78P459AM EM78P459AK EM78P458AP
OCR Text	...KHz * typical of 1 A during the sleep mode 4096 x 13 bits on chip ROM 96 x 8 bits on chip registers (SRAM) 2 bi-directional I/O ports 8 level stacks for subroutine nesting 8-bit real time clock/counter (TCC) with selective signal sources an...
Description	8-bit microprocessors with low-power and high-speed CMOS technology
File Size	258.12K / 44 Page	View it Online	Download Datasheet

				HITACHI[Hitachi Semiconductor]
Part No.	HD74CDCV857
OCR Text	... external RC network required * Sleep mode detection * 48pin TSSOP (Thin Shrink Small Outline Package) HD74CDCV857 Function Table Inputs AV CC GND GND X X 2.5 V 2.5 V 2.5 V H: L: X: Z: Note: PWRDWN CLK H H L L H H X L H L H L H CLK H L...
Description	2.5-V Phase-lock Loop Clock Driver
File Size	60.37K / 15 Page	View it Online	Download Datasheet

				CYPRESS[Cypress Semiconductor]
Part No.	ICY7C1373C-100BGI CY7C1371C CY7C1371C-133AC CY7C1371C-100AC CY7C1371C-100AI CY7C1371C-100BGC CY7C1371C-100BGI CY7C1371C-100BZC CY7C1371C-100BZI CY7C1371C-117AC CY7C1371C-117AI CY7C1371C-117BGC CY7C1371C-117BGI CY7C1371C-117BZC CY7C1371C-117BZI CY7C1371C-133AI CY7C1371C-133BGC CY7C1371C-133BGI CY7C1371C-133BZC CY7C1371C-133BZI CY7C1373C CY7C1373C-100AC CY7C1373C-100AI CY7C1373C-100BGC CY7C1373C-100BZC CY7C1373C-100BZI CY7C1373C-117AC CY7C1373C-117AI CY7C1373C-117BGC CY7C1373C-117BGI CY7C1373C-117BZC CY7C1373C-117BZI CY7C1373C-133AC CY7C1373C-133AI CY7C1373C-133BGC CY7C1373C-133BGI CY7C1373C-133BZC CY7C1373C-133BZI
OCR Text	... INPUT E REGISTER READLOGIC SLEEP CONTROL 2 Logic Block Diagram - CY7C1373C (1M x 18) A0, A1, A MODE CLK CEN C CE ADV/LD C WRITE ADDRESS REGISTER ADDRESS REGISTER A1 D1 A0 D0 Q1 A1' A0' Q0 BURST LOGIC ADV/LD BWA BWB WRITE R...
Description	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL(TM) Architecture 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture
File Size	537.31K / 33 Page	View it Online	Download Datasheet

For sleep-mode Found Datasheets File :: 16115 Search Time::1.875ms
Page :: | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | <9> | 10 | 11 | 12 | 13 | 14 | 15 |