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  pecl lvds Datasheet PDF File

For pecl lvds Found Datasheets File :: 1258    Search Time::1.109ms    
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    Philips
Part No. TZA3017HW
OCR Text ...Positive Emitter Coupled Logic (pecl), Current-Mode Logic (CML) and Low Voltage Differential Signalling (lvds) * Supports co-directional and contra-directional clocking * 4-stage FIFO providing large jitter tolerance on parallel interface *...
Description 30-3200 Mbits/s fibre optic

File Size 150.04K  /  40 Page

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    pmc
Part No. 2000453
OCR Text ...ed inputs and outputs are 3.3 V pecl/CML compatible. * Industrial temperature range (-40 C to +85 C). * 416 pin UBGA package. APPLICATIONS * ATM and Multiservice Switches, Routers, and Switch/Routers. * SONET/SDH Add/Drop Multiplexers w...
Description From old datasheet system

File Size 103.26K  /  2 Page

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    CB65000

ST Microelectronics
STMicroelectronics
Part No. CB65000
OCR Text ... Hard Disk Interface - lvds and pecl for Telecom Standard - PCI for PC Peripheral Interface - USB for Universal Serial Interface 3.4 I/O Test Interface The I/O cells have a dedicated test interface to facilitate parametric and lddq testing ...
Description HCMOS8D 0.18MICRON STANDARD CELLS FAMILY
HCMOS8D 0.18MICRON STANDARD CELLS FAMILY

File Size 564.68K  /  12 Page

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    CYPRESS[Cypress Semiconductor]
Part No. CY2DP814SC CY2DP814 CY2DP814ZIT CY2DP814SCT CY2DP814SI CY2DP814SIT CY2DP814ZC CY2DP814ZCT CY2DP814ZI
OCR Text ...& RTT Figure 1. Differential pecl Output Table 10. High-frequency Parametrics Parameter Fmax Description Maximum Frequency VDD = 3.3V Max...lvds In C o n fig InConfig 0 1 L V D S /L V P E C L LVTTL/LVCMOS Figure 6. [7] Figure...
Description 1:4 Clock Fanout Buffer

File Size 118.91K  /  9 Page

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    Maxim Integrated Products, Inc.
MAXIM - Dallas Semiconductor
Part No. MAX3981
OCR Text ...N-1.0, Interfacing Between CML, pecl, and lvds. The common-mode voltages of the input and output are above 2.5V. ACcoupling capacitors are required when interfacing this part. Values of 0.10F or greater are recommended. General Theory of...
Description 3.125Gbps XAUI Quad Cable Equalizer

File Size 766.90K  /  9 Page

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    Linear
Part No. LTC1748
OCR Text ...y be driven differentially from pecl, GTL and other low swing logic families or from single-ended TTL or CMOS. The low noise, high gain ENC ...lvds. When using a single-ended encode signal asymmetric rise and fall times can result in duty cycl...
Description 5V, 80Msps, Low Noise ADC Parallel Interface

File Size 548.24K  /  20 Page

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    AT84XAD001BTD AT84AD001B AT84AD001BITD AT84AD001BCTD AT84AD001TD-EB

ATMEL[ATMEL Corporation]
Part No. AT84XAD001BTD AT84AD001B AT84AD001BITD AT84AD001BCTD AT84AD001TD-EB
OCR Text ...Differential or Single-ended 50 pecl/lvds Compatible Clock Inputs Power Supply: 3.3V (Analog), 3.3V (Digital), 2.25V (Output) LQFP144 Package Temperature Range: - 0C < TA < 70C (Commercial Grade) - -40C < TA < 85C (Industrial Grade) * 3-wir...
Description Dual 8-bit 1 Gsps ADC

File Size 1,289.34K  /  60 Page

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    MAXIM - Dallas Semiconductor
Part No. MAX3693EVKIT
OCR Text ...rface with lvds inputs and 3.3V pecl outputs. The lvds inputs (PD_+, PD_-, PCLKI+, PCLKI-, RCLK+, RCLK-) are internally terminated with 100 differential input resistance, and therefore do not require external termination. Ensure that lvds d...
Description Evaluation Kit for the MAX3693

File Size 82.00K  /  4 Page

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    P521-29 P521-29DC

PLL[PhaseLink Corporation]
Part No. P521-29 P521-29DC
OCR Text ... VDDANA VDDBUF VDDBUF peclBAR pecl GNDBUF 19 11 20 10 9 8 56.5 mil XOUT OE 21 7 22 1 2 3 4 5 6 GNDOSC GNDANA GNDANA ...lvds differential clock output. X DIE SPECIFICATIONS Name Size Reverse side Pad dimensions Th...
Description Low Phase Noise lvds VCXO (100MHz to 200MHz)

File Size 98.84K  /  6 Page

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For pecl lvds Found Datasheets File :: 1258    Search Time::1.109ms    
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