| Description |
256 Kbit (32K lor='#FF0000'>x lor='#FF0000'>8) nvSRAM; Organization: 32Kb lor='#FF0000'>x lor='#FF0000'>8; Vcc (V): 2.7 to 3.6 V; Density: 256 Kb; Package: SOIC
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 5; Operating Range: 0 to 70 C
256K (32K lor='#FF0000'>x lor='#FF0000'>8) Static RAM; Density: 256 Kb; Organization: 32Kb lor='#FF0000'>x lor='#FF0000'>8; Vcc (V): 4.50 to 5.50 V;
Three-Pll General Purpose FlASH Programmable Clock Generator; Voltage (V): 3.3 V; Input Range: 1 MHz to 166 MHz; Output Range: 1 MHz to 200 MHz; Outputs: 6
5V, 3.3V, ISR(TM) High-Performance CPlDs; # Macrocells: 256; Vcc (V): 3.3; fMalor='#FF0000'>x (MHz): 66; tPD (ns): 12
lor='#FF0000'>8-lor='#FF0000'>mbit (512K lor='#FF0000'>x 16) Static RAM; Density: lor='#FF0000'>8 Mb; Organization: 512Kb lor='#FF0000'>x 16; Vcc (V): 2.20 to 3.60 V;
9-lor='#FF0000'>mbit (256K lor='#FF0000'>x 36/512K lor='#FF0000'>x 1lor='#FF0000'>8) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 9 Mb; Organization: 512Kb lor='#FF0000'>x 1lor='#FF0000'>8; Vcc (V): 3.1 to 3.6 V
9-lor='#FF0000'>mbit (256K lor='#FF0000'>x 36/512K lor='#FF0000'>x 1lor='#FF0000'>8) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 9 Mb; Organization: 512Kb lor='#FF0000'>x 1lor='#FF0000'>8; Vcc (V): 3.1 to 3.6 V
1lor='#FF0000'>8-lor='#FF0000'>mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 1lor='#FF0000'>8 Mb; Organization: 512Kb lor='#FF0000'>x 36; Vcc (V): 1.7 to 1.9 V
Four Output PCI-lor='#FF0000'>x and General Purpose Buffer; Voltage (V): 3.3 V; Frequency Range: 0 MHz to 140 MHz; Outputs: 4; Operating Range: 0 to 70 C
1lor='#FF0000'>8-lor='#FF0000'>mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 1lor='#FF0000'>8 Mb; Organization: 512Kb lor='#FF0000'>x 36; Vcc (V): 1.7 to 1.9 V
9-lor='#FF0000'>mbit (256K lor='#FF0000'>x 36/512K lor='#FF0000'>x 1lor='#FF0000'>8) Flow-Through SRAM with NoBl(TM) Architecture; Architecture: NoBl, Flow-through; Density: 9 Mb; Organization: 512Kb lor='#FF0000'>x 1lor='#FF0000'>8; Vcc (V): 3.1 to 3.6 V
9-lor='#FF0000'>mbit (256K lor='#FF0000'>x 36/512K lor='#FF0000'>x 1lor='#FF0000'>8) Pipelined SRAM with NoBl(TM) Architecture; Architecture: NoBl, Pipeline; Density: 9 Mb; Organization: 512Kb lor='#FF0000'>x 1lor='#FF0000'>8; Vcc (V): 2.4 to 2.6 V
4-lor='#FF0000'>mbit (512K lor='#FF0000'>x lor='#FF0000'>8) Static RAM; Density: 4 Mb; Organization: 512Kb lor='#FF0000'>x lor='#FF0000'>8; Vcc (V): 4.50 to 5.50 V;
4-lor='#FF0000'>mbit (256K lor='#FF0000'>x 16) Static RAM; Density: 4 Mb; Organization: lor='#FF0000'>256kb lor='#FF0000'>x 16; Vcc (V): 2.20 to 3.60 V;
64K lor='#FF0000'>x 16 Static RAM; Density: 1 Mb; Organization: 64Kb lor='#FF0000'>x 16; Vcc (V): 3.0 to 3.6 V;
1-lor='#FF0000'>mbit (64K lor='#FF0000'>x 16) Static RAM; Density: 1 Mb; Organization: 64Kb lor='#FF0000'>x 16; Vcc (V): 4.5 to 5.5 V;
9-lor='#FF0000'>mbit (256K lor='#FF0000'>x 36/512K lor='#FF0000'>x 1lor='#FF0000'>8) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 9 Mb; Organization: lor='#FF0000'>256kb lor='#FF0000'>x 36; Vcc (V): 3.1 to 3.6 V
1-lor='#FF0000'>mbit (64K lor='#FF0000'>x 16) Static RAM; Density: 1 Mb; Organization: 64Kb lor='#FF0000'>x 16; Vcc (V): 3.0 to 3.6 V;
4 lor='#FF0000'>mbit (512K lor='#FF0000'>x lor='#FF0000'>8/256K lor='#FF0000'>x 16) nvSRAM; Organization: 512Kb lor='#FF0000'>x lor='#FF0000'>8; Vcc (V): 2.7 to 3.6 V; Density: 4 Mb; Package: TSOP
4 lor='#FF0000'>mbit (512K lor='#FF0000'>x lor='#FF0000'>8/256K lor='#FF0000'>x 16) nvSRAM; Organization: lor='#FF0000'>256kb lor='#FF0000'>x 16; Vcc (V): 2.7 to 3.6 V; Density: 4 Mb; Package: TSOP
16-lor='#FF0000'>mbit (1M lor='#FF0000'>x 16 / 2M lor='#FF0000'>x lor='#FF0000'>8) Static RAM; Density: 16 Mb; Organization: 1Mb lor='#FF0000'>x 16; Vcc (V): 4.50 to 5.50 V;
4K lor='#FF0000'>x 16/1lor='#FF0000'>8 and lor='#FF0000'>8K lor='#FF0000'>x 16/1lor='#FF0000'>8 Dual-Port Static RAM with SEM, INT, BUSY; Density: 12lor='#FF0000'>8 Kb; Organization: lor='#FF0000'>8Kb lor='#FF0000'>x 16; Vcc (V): 4.5 to 5.5 V; Speed: 35 ns
9-lor='#FF0000'>mbit (256K lor='#FF0000'>x 36/512K lor='#FF0000'>x 1lor='#FF0000'>8) Pipelined SRAM with NoBl(TM) Architecture; Architecture: NoBl, Pipeline; Density: 9 Mb; Organization: lor='#FF0000'>256kb lor='#FF0000'>x 36; Vcc (V): 3.1 to 3.6 V
9-lor='#FF0000'>mbit (256K lor='#FF0000'>x 36/512K lor='#FF0000'>x 1lor='#FF0000'>8) Flow-Through SRAM with NoBl(TM) Architecture; Architecture: NoBl, Flow-through; Density: 9 Mb; Organization: lor='#FF0000'>256kb lor='#FF0000'>x 36; Vcc (V): 3.1 to 3.6 V
9-lor='#FF0000'>mbit (256K lor='#FF0000'>x 36/512K lor='#FF0000'>x 1lor='#FF0000'>8) Pipelined SRAM with NoBl(TM) Architecture; Architecture: NoBl, Pipeline; Density: 9 Mb; Organization: lor='#FF0000'>256kb lor='#FF0000'>x 36; Vcc (V): 2.4 to 2.6 V
9-lor='#FF0000'>mbit (256K lor='#FF0000'>x 36/512K lor='#FF0000'>x 1lor='#FF0000'>8) Pipelined SRAM with NoBl(TM) Architecture; Architecture: NoBl, Pipeline; Density: 9 Mb; Organization: 512Kb lor='#FF0000'>x 1lor='#FF0000'>8; Vcc (V): 3.1 to 3.6 V
lor='#FF0000'>8-lor='#FF0000'>mbit (512K lor='#FF0000'>x 16) Static RAM; Density: lor='#FF0000'>8 Mb; Organization: 512Kb lor='#FF0000'>x 16; Vcc (V): 4.50 to 5.50 V;
9-lor='#FF0000'>mbit (256K lor='#FF0000'>x 36/512K lor='#FF0000'>x 1lor='#FF0000'>8) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 9 Mb; Organization: lor='#FF0000'>256kb lor='#FF0000'>x 36; Vcc (V): 3.1 to 3.6 V
256K lor='#FF0000'>x 16 Static RAM; Density: 4 Mb; Organization: lor='#FF0000'>256kb lor='#FF0000'>x 16; Vcc (V): 4.5 to 5.5 V;
9-lor='#FF0000'>mbit (256K lor='#FF0000'>x 36/512K lor='#FF0000'>x 1lor='#FF0000'>8) Pipelined DCD Sync SRAM; Architecture: Standard Sync, Pipeline DCD; Density: 9 Mb; Organization: lor='#FF0000'>256kb lor='#FF0000'>x 36; Vcc (V): 3.1 to 3.6 V
4-lor='#FF0000'>mbit (256K lor='#FF0000'>x 16) Static RAM; Density: 4 Mb; Organization: lor='#FF0000'>256kb lor='#FF0000'>x 16; Vcc (V): 3.0 to 3.6 V;
lor='#FF0000'>8-lor='#FF0000'>mbit (1024K lor='#FF0000'>x lor='#FF0000'>8) Static RAM; Density: lor='#FF0000'>8 Mb; Organization: 1Mb lor='#FF0000'>x lor='#FF0000'>8; Vcc (V): 2.20 to 3.60 V;
1lor='#FF0000'>8-lor='#FF0000'>mbit (512K lor='#FF0000'>x 36/1M lor='#FF0000'>x 1lor='#FF0000'>8) Pipelined SRAM with NoBl(TM) Architecture; Architecture: NoBl, Pipeline; Density: 1lor='#FF0000'>8 Mb; Organization: 512Kb lor='#FF0000'>x 36; Vcc (V): 3.1 to 3.6 V
256K lor='#FF0000'>x 16 Static RAM; Density: 4 Mb; Organization: lor='#FF0000'>256kb lor='#FF0000'>x 16; Vcc (V): 3.0 to 3.6 V;
lor='#FF0000'>8-lor='#FF0000'>mbit (1M lor='#FF0000'>x lor='#FF0000'>8) Static RAM; Density: lor='#FF0000'>8 Mb; Organization: 1Mb lor='#FF0000'>x lor='#FF0000'>8; Vcc (V): 2.20 to 3.60 V;
3.3V Zero Delay Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: lor='#FF0000'>8; Operating Range: -40 to lor='#FF0000'>85 C
Programmable Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to lor='#FF0000'>80 MHz; Outputs: lor='#FF0000'>8; Operating Range: -40 to lor='#FF0000'>85 C
1lor='#FF0000'>8-lor='#FF0000'>mbit (512K lor='#FF0000'>x 36/1M lor='#FF0000'>x 1lor='#FF0000'>8) Flow-Through SRAM with NoBl(TM) Architecture; Architecture: NoBl, Flow-through; Density: 1lor='#FF0000'>8 Mb; Organization: 512Kb lor='#FF0000'>x 36; Vcc (V): 3.1 to 3.6 V
1lor='#FF0000'>8-lor='#FF0000'>mbit (512K lor='#FF0000'>x 36/1M lor='#FF0000'>x 1lor='#FF0000'>8) Pipelined SRAM with NoBl(TM) Architecture; Architecture: NoBl, Pipeline; Density: 1lor='#FF0000'>8 Mb; Organization: 1Mb lor='#FF0000'>x 1lor='#FF0000'>8; Vcc (V): 3.1 to 3.6 V
512K lor='#FF0000'>x lor='#FF0000'>8 Static RAM; Density: 4 Mb; Organization: 512Kb lor='#FF0000'>x lor='#FF0000'>8; Vcc (V): 4.5 to 5.5 V;
1lor='#FF0000'>8-lor='#FF0000'>mbit (512K lor='#FF0000'>x 36/1M lor='#FF0000'>x 1lor='#FF0000'>8) Pipelined SRAM with NoBl(TM) Architecture; Architecture: NoBl, Pipeline; Density: 1lor='#FF0000'>8 Mb; Organization: 512Kb lor='#FF0000'>x 36; Vcc (V): 2.4 to 2.6 V
2.5V or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 MHz to 200 MHz; Outputs: 12; Operating Range: -40 to lor='#FF0000'>85 C
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 5; Operating Range: -40 to lor='#FF0000'>85 C
2M lor='#FF0000'>x lor='#FF0000'>8 Static RAM; Density: 16 Mb; Organization: 2Mb lor='#FF0000'>x lor='#FF0000'>8; Vcc (V): 3.0 to 3.6 V;
16 lor='#FF0000'>mbit (512K lor='#FF0000'>x 32) Static RAM; Density: 16 Mb; Organization: 512Kb lor='#FF0000'>x 32; Vcc (V): 3.0 to 3.6 V;
3.3V Zero Delay Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: lor='#FF0000'>8; Operating Range: 0 to 70 C
lor='#FF0000'>8-lor='#FF0000'>mbit (1M lor='#FF0000'>x lor='#FF0000'>8) Static RAM; Density: lor='#FF0000'>8 Mb; Organization: 1Mb lor='#FF0000'>x lor='#FF0000'>8; Vcc (V): 3.0 to 3.6 V;
5V, 3.3V, ISR(TM) High-Performance CPlDs; # Macrocells: 64; Vcc (V): 5; fMalor='#FF0000'>x (MHz): 125; tPD (ns): 6
2-lor='#FF0000'>mbit (12lor='#FF0000'>8K lor='#FF0000'>x 16) Static RAM; Density: 2 Mb; Organization: 12lor='#FF0000'>8Kb lor='#FF0000'>x 16; Vcc (V): 3.0 to 3.6 V;
16-lor='#FF0000'>mbit (1M lor='#FF0000'>x 16) Static RAM; Density: 16 Mb; Organization: 1Mb lor='#FF0000'>x 16; Vcc (V): 3.0 to 3.6 V;
4-lor='#FF0000'>mbit (256K lor='#FF0000'>x 1lor='#FF0000'>8) Pipelined DCD Sync SRAM; Architecture: Standard Sync, Pipeline DCD; Density: 4 Mb; Organization: lor='#FF0000'>256kb lor='#FF0000'>x 1lor='#FF0000'>8; Vcc (V): 3.1 to 3.6 V
512K (32K lor='#FF0000'>x 16) Static RAM; Density: 512 Kb; Organization: 32Kb lor='#FF0000'>x 16; Vcc (V): 3.0 to 3.6 V;
4-lor='#FF0000'>mbit (12lor='#FF0000'>8K lor='#FF0000'>x 36) Pipelined SRAM with NoBl(TM) Architecture; Architecture: NoBl, Pipeline; Density: 4 Mb; Organization: 12lor='#FF0000'>8Kb lor='#FF0000'>x 36; Vcc (V): 3.1 to 3.6 V
1M lor='#FF0000'>x 16 Static RAM; Density: 16 Mb; Organization: 1Mb lor='#FF0000'>x 16; Vcc (V): 3.0 to 3.6 V;
Programmable Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to lor='#FF0000'>80 MHz; Outputs: lor='#FF0000'>8; Operating Range: 0 to 70 C
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 9; Operating Range: 0 to 70 C
MoBl(R) 2 lor='#FF0000'>mbit (12lor='#FF0000'>8K lor='#FF0000'>x 16) Static RAM; Density: 2 Mb; Organization: 12lor='#FF0000'>8Kb lor='#FF0000'>x 16; Vcc (V): 2.20 to 3.60 V;
Rambus(R) lor='#FF0000'>xDR(TM) Clock Generator; VDD: 2.5 V; Input Frequency: 100 MHz to 133 MHz; Output Frequency: 300 MHz to lor='#FF0000'>800 MHz; # Out: 4
2-lor='#FF0000'>mbit (12lor='#FF0000'>8K lor='#FF0000'>x 16) Static RAM; Density: 2 Mb; Organization: 12lor='#FF0000'>8Kb lor='#FF0000'>x 16; Vcc (V): 2.20 to 3.60 V;
4-lor='#FF0000'>mbit (12lor='#FF0000'>8K lor='#FF0000'>x 36) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 4 Mb; Organization: 12lor='#FF0000'>8Kb lor='#FF0000'>x 36; Vcc (V): 3.1 to 3.6 V
5V, 3.3V, ISR(TM) High-Performance CPlDs; # Macrocells: 12lor='#FF0000'>8; Vcc (V): 5; fMalor='#FF0000'>x (MHz): 167; tPD (ns): 7
2.5V or 3.3V, 200-MHz, 1:10 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 MHz to 200 MHz; Outputs: 10; Operating Range: 0 to 70 C
5V, 3.3V, ISR(TM) High-Performance CPlDs; # Macrocells: 12lor='#FF0000'>8; Vcc (V): 5; fMalor='#FF0000'>x (MHz): 100; tPD (ns): 7
5V, 3.3V, ISR(TM) High-Performance CPlDs; # Macrocells: 12lor='#FF0000'>8; Vcc (V): 5; fMalor='#FF0000'>x (MHz): 125; tPD (ns): 7
1lor='#FF0000'>8-lor='#FF0000'>mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 1lor='#FF0000'>8 Mb; Organization: 512Kb lor='#FF0000'>x 36; Vcc (V): 1.7 to 1.9 V
low Voltage Programmable Skew Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 3.75 MHz to lor='#FF0000'>80 MHz; Outputs: lor='#FF0000'>8; Operating Range: 0 to 70 C
Spread Spectrum Clock Generator; Voltage(V): 3.3 V; Input Frequency Range: 25 MHz to 100 MHz; Output Frequency Range: 25 MHz to 100 MHz; Operating Range: 0 to 70 C; Package: SOIC
low Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to lor='#FF0000'>80 MHz; Outputs: lor='#FF0000'>8; Operating Range: 0 to 70 C
5V, 3.3V, ISR(TM) High-Performance CPlDs; # Macrocells: 64; Vcc (V): 3.3; fMalor='#FF0000'>x (MHz): 143; tPD (ns): 9 单芯位CMOS微机
5V, 3.3V, ISR(TM) High-Performance CPlDs; # Macrocells: 64; Vcc (V): 5; fMalor='#FF0000'>x (MHz): 154; tPD (ns): 6 单芯位CMOS微机
SINGlE-CHIP lor='#FF0000'>8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机
5V, 3.3V, ISR(TM) High-Performance CPlDs; # Macrocells: 64; Vcc (V): 3.3; fMalor='#FF0000'>x (MHz): 100; tPD (ns): 9 单芯位CMOS微机
5V, 3.3V, ISR(TM) High-Performance CPlDs; # Macrocells: 12lor='#FF0000'>8; Vcc (V): 3.3; fMalor='#FF0000'>x (MHz): lor='#FF0000'>83; tPD (ns): 10 单芯位CMOS微机
5V, 3.3V, ISR(TM) High-Performance CPlDs; # Macrocells: 64; Vcc (V): 5; fMalor='#FF0000'>x (MHz): 125; tPD (ns): 6 单芯位CMOS微机
Three-Pll General-Purpose EPROM Programmable Clock Generator; Voltage (V): 3.3/5.0 V; Input Range: 1 MHz to 30 MHz; Output Range: .077 MHz to 100 MHz; Outputs: 6 单芯位CMOS微机
lor='#FF0000'>8-lor='#FF0000'>mbit (512K lor='#FF0000'>x 16) MoBl(R) Static RAM; Density: lor='#FF0000'>8 Mb; Organization: 512Kb lor='#FF0000'>x 16; Vcc (V): 2.20 to 3.60 V; 单芯位CMOS微机
High Speed low Voltage Programmable Skew Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 3.75 MHz to 110 MHz; Outputs: lor='#FF0000'>8; Operating Range: 0 to 70 C 单芯位CMOS微机
3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs; Voltage (V): 3.3 V; Frequency Range: 0 MHz to 100 MHz; Outputs: 10; Operating Range: 0 to 70 C 单芯位CMOS微机
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 9; Operating Range: -40 to lor='#FF0000'>85 C 单芯位CMOS微机
Programmable Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to lor='#FF0000'>80 MHz; Outputs: lor='#FF0000'>8; Operating Range: -40 to lor='#FF0000'>85 C 单芯位CMOS微机
2-lor='#FF0000'>mbit (12lor='#FF0000'>8K lor='#FF0000'>x 16) Static RAM; Density: 2 Mb; Organization: 12lor='#FF0000'>8Kb lor='#FF0000'>x 16; Vcc (V): 3.0 to 3.6 V; 单芯位CMOS微机
MoBl(R) 1 lor='#FF0000'>mbit (12lor='#FF0000'>8K lor='#FF0000'>x lor='#FF0000'>8) Static RAM; Density: 1 Mb; Organization: 12lor='#FF0000'>8Kb lor='#FF0000'>x lor='#FF0000'>8; Vcc (V): 2.20 to 3.60 V; 单芯位CMOS微机
1lor='#FF0000'>8-lor='#FF0000'>mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 1lor='#FF0000'>8 Mb; Organization: 1Mb lor='#FF0000'>x 1lor='#FF0000'>8; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
1-lor='#FF0000'>mbit (12lor='#FF0000'>8K lor='#FF0000'>x lor='#FF0000'>8) Static RAM; Density: 1 Mb; Organization: 12lor='#FF0000'>8Kb lor='#FF0000'>x lor='#FF0000'>8; Vcc (V): 4.50 to 5.50 V; 单芯位CMOS微机
4-lor='#FF0000'>mbit (256K lor='#FF0000'>x 1lor='#FF0000'>8) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 4 Mb; Organization: lor='#FF0000'>256kb lor='#FF0000'>x 1lor='#FF0000'>8; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
2-lor='#FF0000'>mbit (64K lor='#FF0000'>x 32) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 2 Mb; Organization: 64Kb lor='#FF0000'>x 32; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
200-MHz Field Programmable Zero Delay Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 10 MHz to 200 MHz; Outputs: 12; Operating Range: -40 to lor='#FF0000'>85 C 单芯位CMOS微机
2-lor='#FF0000'>mbit (12lor='#FF0000'>8K lor='#FF0000'>x 16) Static RAM; Density: 2 Mb; Organization: 12lor='#FF0000'>8Kb lor='#FF0000'>x 16; Vcc (V): 2.20 to 3.60 V; 单芯位CMOS微机
SINGlE-CHIP lor='#FF0000'>8-BIT CMOS MICROCOMPUTER 单芯lor='#FF0000'>8位CMOS微机
2-lor='#FF0000'>mbit (256K lor='#FF0000'>x lor='#FF0000'>8) Static RAM; Density: 2 Mb; Organization: lor='#FF0000'>256kb lor='#FF0000'>x lor='#FF0000'>8; Vcc (V): 2.20 to 3.60 V; 单芯lor='#FF0000'>8位CMOS微机
Very low Jitter Field and Factory Programmable Clock Generator; Voltage (V): 3.3 V; Input Range: 10 MHz to 133 MHz; Output Range: 20 MHz to 200 MHz; Outputs: 2 单芯位CMOS微机
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 5; Operating Range: 0 to 70 C 单芯位CMOS微机
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 5; Operating Range: -40 to lor='#FF0000'>85 C 单芯位CMOS微机
Three-Pll General Purpose FlASH Programmable Clock Generator; Voltage (V): 3.3 V; Input Range: 1 MHz to 166 MHz; Output Range: 0 MHz to 200 MHz; Outputs: 3 单芯位CMOS微机
1:lor='#FF0000'>8 Clock Fanout Buffer; Voltage (V): 3.3 V; Frequency Range: 0 MHz to 350 MHz; Outputs: lor='#FF0000'>8; Operating Range: -40 to lor='#FF0000'>85 C 单芯位CMOS微机
Quad Pll Clock Generator with 2-Wire Serial Interface; Voltage (V): 2.5/3.3 V; Input Range: 27 MHz to 27 MHz; Output Range: 4.2 MHz to 166 MHz; Outputs: 5 单芯位CMOS微机
2.5V or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 MHz to 200 MHz; Outputs: 12; Operating Range: 0 to 70 C 单芯位CMOS微机
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 9; Operating Range: 0 to 70 C 单芯位CMOS微机
High Speed Multi-phase Pll Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 24 MHz to 200 MHz; Outputs: 11; Operating Range: 0 to 70 C 单芯位CMOS微机
2.5V or 3.3V, 200-MHz, 1:1lor='#FF0000'>8 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 MHz to 200 MHz; Outputs: 1lor='#FF0000'>8; Operating Range: -40 to lor='#FF0000'>85 C 单芯位CMOS微机
-bit AVR Microcontroller with lor='#FF0000'>8K Bytes In- System Programmable Flash 位AVR微控制器具有lor='#FF0000'>8K字节的系统内可编程闪
2.5V or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 MHz to 200 MHz; Outputs: 12; Operating Range: 0 to 70 C
1:lor='#FF0000'>8 Clock Fanout Buffer; Voltage (V): 3.3 V; Frequency Range: 0 MHz to 350 MHz; Outputs: lor='#FF0000'>8; Operating Range: 0 to 70 C
Spread Spectrum Clock Generator; Voltage(V): 3.3 V; Input Frequency Range: 4 MHz to 32 MHz; Output Frequency Range: 4 MHz to 32 MHz; Operating Range: 0 to 70 C; Package: SOIC
High Speed low Voltage Programmable Skew Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 3.75 MHz to 110 MHz; Outputs: lor='#FF0000'>8; Operating Range: 0 to 70 C
5V, 3.3V, ISR(TM) High-Performance CPlDs; # Macrocells: 64; Vcc (V): 3.3; fMalor='#FF0000'>x (MHz): 100; tPD (ns): 9
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