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SMSC
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| Part No. |
LAN9215
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| OCR Text |
efficient 10/100 Ethernet Controller with HP Auto-MDIX
PRODUCT FEATURES
Highlights
Optimized for medium performance applications efficient architecture with low CPU overhead Easily interfaces to most 16-bit embedded CPU's Integrated PH... |
| Description |
Highly efficient 10/100 Ethernet Controller with HP Auto-MDIX
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| File Size |
929.45K /
136 Page |
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it Online |
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| Part No. |
4610-2RD
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| OCR Text |
...PS), Dual Harvard DSP core with efficient scatter-gather DMA controller. -- Multiple audio stream mixing and sample rate conversion for 2D and 3D positional audio data. -- Accelerates DirectSound(R), DirectSound3D(R), DirectShow(R) and Aure... |
| Description |
From old datasheet system
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| File Size |
427.28K /
16 Page |
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it Online |
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| Part No. |
AT94K
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| OCR Text |
...lting architecture is more code-efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers at the same clock frequency. The AVR executes out of on-chip SRAM. Both the FPGA configuration SRAM and the... |
| Description |
From old datasheet system
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| File Size |
126.00K /
6 Page |
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it Online |
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| Part No. |
ATF1502
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| OCR Text |
...sability. Atmel's commitment to efficient, flexible architecture has continued with the current Atmel ATF15xx Family of industry-standard, pin-compatible CPLDs. Atmel's Logic Doubling architecture consists of wider fan-in, additional routin... |
| Description |
From old datasheet system
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| File Size |
597.78K /
76 Page |
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it Online |
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| Part No. |
DSP56852
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| OCR Text |
...Digital Signal Processing Core
efficient 16-bit DSP engine with dual Harvard architecture 120 Million Instructions Per Second (MIPS) at 120MHz core frequency Single-cycle 16 x 16-bit parallel Multiplier-Accumulator (MAC) Four (4) 36-bit ac... |
| Description |
From old datasheet system
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| File Size |
480.56K /
44 Page |
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it Online |
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| Part No. |
DSP56853
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| OCR Text |
...Digital Signal Processing Core
efficient 16-bit DSP engine with dual Harvard architecture 120 Million Instructions Per Second (MIPS) at 120MHz core frequency Single-cycle 16 x 16-bit parallel Multiplier-Accumulator (MAC) Four (4) 36-bit ac... |
| Description |
From old datasheet system
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| File Size |
542.86K /
48 Page |
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it Online |
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Motorola
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| Part No. |
DSP56855
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| OCR Text |
...Digital Signal Processing Core
efficient 16-bit DSP engine with dual Harvard architecture 120 Million Instructions Per Second (MIPS) at 120MHz core frequency Single-cycle 16 x 16-bit parallel Multiplier-Accumulator (MAC) Four (4) 36-bit ac... |
| Description |
DSP56855 16-Bit Digital Signal Processors
From old datasheet system
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| File Size |
368.12K /
44 Page |
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it Online |
Download Datasheet |
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Motorola
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| Part No. |
DSP56857
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| OCR Text |
...Digital Signal Processing Core
efficient 16-bit DSP engine with dual Harvard architecture 120 Million Instructions Per Second (MIPS) at 120MHz core frequency Single-cycle 16 x 16-bit parallel Multiplier-Accumulator (MAC) Four (4)36-bit acc... |
| Description |
DSP56857 16-Bit digital Signal Processor
From old datasheet system
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| File Size |
430.01K /
48 Page |
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it Online |
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| Part No. |
DSP56F801
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| OCR Text |
...U functionality in a unified, C-efficient architecture MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes 8K x 16-bit words Program Flash 1K x 16-bit words Program RAM 2K... |
| Description |
From old datasheet system
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| File Size |
368.27K /
42 Page |
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it Online |
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