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pll-output Datasheet PDF File

For pll-output Found Datasheets File :: 23234 Search Time::2.656ms
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				Integrated Device Technology
Part No.	DAC1627D1G25
OCR Text	... integrated phase-locked loop (pll) multiplier which generates a dac clock rate from the lvds clock rate. the dac1627d1g25 is available i...output current from 8.1 ma to 34 ma ? low noise capacitor-free integrated phase-locked loop (pll) ...
Description	Dual 16-bit DAC, LVDS interface, up to 1.25 Gsps, x2, x4 and x8 interpolating
File Size	1,555.03K / 81 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C2568XV18-600BZXC CY7C2570XV18-600BZXC CY7C2568XV1812 CY7C2568XV18-633BZXC
OCR Text	...access port phase-locked loop (pll) for accurate data placement configurations with read cycle latency of 2.5 cycles: cy7c2568xv18 ? 4 m 1...output impedance matching input (zq). synchronous data outputs (q, sharing the same physical pins as...
Description	72-Mbit DDR II Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
File Size	646.33K / 29 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C2565XV18-600BZC CY7C2565XV18-600BZXC CY7C2565XV18-633BZC CY7C2563XV18-633BZC CY7C2563XV18-600BZXC CY7C2563XV18-600BZC CY7C2563XV18-633BZXC
OCR Text	...access port phase-locked loop (pll) for accurate data placement configurations with read cycle latency of 2.5 cycles cy7c2563xv18 ? 4 m 18...output registers controlled by the k or k input clocks. writes are conducted with on-chip synchron ...
Description	72-Mbit QDR? II Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
File Size	590.53K / 29 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1568XV18-600BZXC CY7C1570XV18-600BZXC CY7C1568XV18-633BZXC
OCR Text	...access port phase-locked loop (pll) for accurate data placement configurations with read cycle latency of 2.5 cycles: cy7c1568xv18 ? 4 m 1...output impedance matching input (zq). synchronous data outputs (q, sharing the same physical pins as...
Description	72-Mbit DDR II Xtreme SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
File Size	440.08K / 27 Page	View it Online	Download Datasheet

				Mitel Semiconductor MITEL[Mitel Networks Corporation]
Part No.	MT8940-1 MT8940AE
OCR Text	PLL Features * * Provides T1 clock at 1.544 MHz locked to input frame pulse Sources CEPT (30+2) Digital Trunk/ST-BUS clock and timing si...output and when LOW, it is in high impedance state. However, if MS1 is HIGH, CVb is always an input....
Description	ISO-CMOS ST-BUS FAMILY T1/CEPT Digital Trunk PLL ISO-CMOS ST-BUS⑩ FAMILY T1/CEPT Digital Trunk PLL
File Size	132.04K / 19 Page	View it Online	Download Datasheet

				Mitel Semiconductor MITEL[Mitel Networks Corporation]
Part No.	MT8940AC MT8940AE
OCR Text	PLL Features * * Provides T1 clock at 1.544 MHz locked to input frame pulse Sources CEPT (30+2) Digital Trunk/ST-BUS clock and timing si...output and when LOW, it is in high impedance state. However, if MS1 is HIGH, CVb is always an input....
Description	T1/CEPT Digital Trunk PLL
File Size	204.10K / 16 Page	View it Online	Download Datasheet

				MITEL[Mitel Networks Corporation]
Part No.	MT8940 MT8940AE
OCR Text	PLL Features * * Provides T1 clock at 1.544 MHz locked to input frame pulse Sources CEPT (30+2) Digital Trunk/ST-BUS clock and timing si...output and when LOW, it is in high impedance state. However, if MS1 is HIGH, CVb is always an input....
Description	ISO-CMOS ST-BUSFAMILY T1/CEPT Digital Trunk PLL ISO-CMOS ST-BUS FAMILY T1/CEPT Digital Trunk PLL ISO-CMOS ST-BUS⑩ FAMILY T1/CEPT Digital Trunk PLL
File Size	116.52K / 16 Page	View it Online	Download Datasheet

				MITEL[Mitel Networks Corporation]
Part No.	MT8941B MT8941BE MT8941BP
OCR Text	PLL Features * * Provides T1 clock at 1.544 MHz locked to an 8 kHz reference clock (frame pulse) Provides CEPT clock at 2.048 MHz and ST...output jitter (unfiltered)= 0.07 UI peak-to-peak Typical jitter attenuation at: 10 Hz=23 dB,100 Hz=4...
Description	CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL CMOS ST-BUS FAMILY Advanced T1/CEPT Digital Trunk PLL
File Size	130.44K / 22 Page	View it Online	Download Datasheet

				MITEL[Mitel Networks Corporation]
Part No.	MT8941 MT8941AE MT8941AP
OCR Text	PLL Features * * Provides T1 clock at 1.544 MHz locked to an 8 kHz reference clock (frame pulse) Provides CEPT clock at 2.048 MHz and ST...output jitter (unfiltered)= 0.07 UI peak-to-peak Typical jitter attenuation at: 10 Hz=23 dB,100 Hz=4...
Description	CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL CMOS ST-BUS FAMILY Advanced T1/CEPT Digital Trunk PLL
File Size	246.12K / 18 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1564XV18-366BZC CY7C1562XV18-366BZXC CY7C1562XV18-450BZC CY7C1564XV18-450BZC CY7C1562XV18-450BZXC CY7C1564XV18-450BZXC CY7C1564XV18-366BZXC CY7C1562XV18-366BZC
OCR Text	...access port phase-locked loop (pll) for accurate data placement configurations with read cycle latency of 2.5 cycles: cy7c1562xv18 ? 4 m 1...output registers controlled by the k or k input clocks. writes are conducted with on-chip synchrono...
Description	72-Mbit QDR? II Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
File Size	632.54K / 29 Page	View it Online	Download Datasheet

For pll-output Found Datasheets File :: 23234 Search Time::2.656ms
Page :: | 1 | 2 | 3 | 4 | 5 | 6 | 7 | <8> | 9 | 10 | 11 | 12 | 13 | 14 | 15 |