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  dpll Datasheet PDF File

For dpll Found Datasheets File :: 819    Search Time::2.125ms    
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    MB86H20

Fujitsu Microelectronics
Fujitsu Media Devices Limited
Fujitsu Component Limited.
Part No. MB86H20
OCR Text ...n integrated S/P-DIF interface, dpll, and internal audio DAC's. This helps to reduce product cost by eliminating the need for external components. The SmartMPEG adds also dpll functionality, SECAM encoding, and two Smart-card interface to f...
Description SmartMPEG

File Size 171.77K  /  2 Page

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    Siemens
Part No. SAF82520-N SAF82520-P
OCR Text ...rmed by an on- chip oscillator, dpll circuits and a programmable baudrate generator. type ordering code package sab 82520-n q67100-h8400 p-lcc-28 (smd ) sab 82520-p q67100-h8014 p-dip-28 saf 82520-n q67100-h8610 p-lcc-28 (smd) sa...
Description High-Level Serial Communications Controller

File Size 366.38K  /  53 Page

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    MT8941AP MT8941APR

ZARLINK SEMICONDUCTOR INC
Part No. MT8941AP MT8941APR
OCR Text ...ck control mode selection logic dpll #2 input selector clock generator frame pulse control 4.096 mhz clock control 2.048 mhz clock control dpll #1 issue 5 july 1993 mt8941 advanced t1/cept digital trunk pll cmos st-bus ? family mt8941 c...
Description SPECIALTY TELECOM CIRCUIT, PQCC28

File Size 556.90K  /  24 Page

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    ZL50010 ZL50010_GDC ZL50010_QCC

ZARLINK[Zarlink Semiconductor Inc]
Part No. ZL50010 ZL50010_GDC ZL50010_QCC
OCR Text dpll Data Sheet Features * 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation Rate conversion between the ST-BUS inputs and ST-BUS outputs Integrated Digital Phase-Locked Loop (dpll) meets Telc...
Description Flexible 512 Channel DX with Enhanced dpll

File Size 672.90K  /  86 Page

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    Integrated Device Technology, Inc.
Integrated Circuit Syst...
Part No. IDT82P33731
OCR Text ...the active refer- ence for each dpll based on the reference monitors, priority tables, revertive and non-revertive settings and other programmable settings ? fractional-n input dividers enable the dplls to lock to a wide range of referenc...
Description Synchronous Equipment Timing Source for 10G-40G Synchronous Ethernet
Composite clock inputs

File Size 193.37K  /  12 Page

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    LSI CORP
Part No. T8100A--BAL3-DB T8105---BAL3-BB T8102---BAL3-DB T8100A--SC3-DB
OCR Text ... 4.096 mhz in the digital pll (dpll). the dpll introduces sufficient jitter on the a or b master output clocks that slave devices falsely interpret as a loss of sync and either snap or slide align to this false sync indication. this, i...
Description DATACOM, TIME SLOT ASSIGNER, PBGA217
DATACOM, TIME SLOT ASSIGNER, PQFP208

File Size 1,371.38K  /  112 Page

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    Electronic Theatre Controls, Inc.
Part No. RTD2513
OCR Text ... / v [ 6 ] / d v s xo xi dpll_gnd apll_gnd pll_tst2 pll_tst1 apll_vdd dpll_vdd b+ r- b- g- r+ adc_vdd g+ sog adc_gnd adc_vdd adc_gnd adc_refio b b 3 p b b 3 n t c o n [ 1 2 ] / c o u t / p w m 2 t c o n [ 1 0 ] / v [ 1 ] t c o n ...
Description Flat Panel Display Controller

File Size 816.54K  /  129 Page

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    IDT
Part No. IDT82V3001A
OCR Text ...ns a Digital Phase-Locked Loop (dpll), which generates ST-BUS clocks and framing signals that are phase locked to a 2.048 MHz, 1.544 MHz or 8 kHz input reference. The IDT82V3001A provides eight types of clock signals (C1.5o, C3o, C6o, C2o, ...
Description WAN PLL WITH SINGLE REFERENCE INPUT

File Size 317.04K  /  27 Page

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For dpll Found Datasheets File :: 819    Search Time::2.125ms    
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