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Philips
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| Part No. |
TZA3012AHW
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| OCR Text |
...TYQ
LOS
TZA3012AHW
c d dmx 1 : 4 16 1:8 1 : 10 1 : 16
PARITY GENERATOR AND BUS SWAP
16
D00 to D15
SWITCH
PHASE 2 DETECTOR 2 2 2
d c
16
45, 47, 49, 54 56, 58, 60, 62, 65, 67, 69, 71 73, 78, 80, 82
D00Q to ... |
| Description |
30 Mbits/s up to 3.2 Gbits/s
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| File Size |
207.23K /
52 Page |
 View
it Online |
Download Datasheet
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Cypress Semiconductor, Corp.
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| Part No. |
MT8HTF25664HZ-1GAXX MT8HTF12864HZ-1GAXX
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| OCR Text |
...y and clocks on the ddr2 sdram. dmx, input data mask (x8 devices only): dm is an input mask signal for write data. input data is masked when dm is sampled high, along with that input data, during a write ac- cess. although dm pins are inpu... |
| Description |
256M X 64 DDR DRAM MODULE, ZMA200 HALOGEN FREE, MO-224, SODIMM-200
128M X 64 DDR DRAM MODULE, ZMA200 HALOGEN FREE, MO-224, SODIMM-200
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| File Size |
307.57K /
14 Page |
View
it Online |
Download Datasheet |
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Philips
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| Part No. |
TZA3012AHW TZA3012AHW/N1
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| OCR Text |
...4 85 91 523031 34 27 2 2 390 32 dmx 1 : 4 1 : 8 1 : 10 1 : 16 parity generator and bus swap d00 to d15 parity parityq d00q to d15q poclk inwindow enloutq winsize crefq prscloq los2 rssi2 cref prsclo i.c. rref ui cs(dr0) sda(dr1) scl(dr2) lo... |
| Description |
TZA3012AHW; 30 Mbits/s up to 3.2 Gbits/s A-rate (tm) fibre optic receiver
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| File Size |
239.86K /
60 Page |
View
it Online |
Download Datasheet |
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Vitesse Semiconductor, Corp.
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| Part No. |
VSC8151QV
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| OCR Text |
...ce terminated 2.488gb/s i/o 1:8 dmx framing control & alarm detection rxsin+/- rxsclkin+/- descrambler rxsef rxfpout rxfrerr rxlof b1 monitor overhead output rxohclk rxohout[7:0] overhead input & internal control txohin[7:0] ais generation ... |
| Description |
2.488Gb/s SONET/SDH STS-48/STM-16 Section Terminator TERMINATOR, PQFP160
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| File Size |
477.06K /
30 Page |
View
it Online |
Download Datasheet |
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Cypress Semiconductor, Corp.
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| Part No. |
MT18HTF25672AIZ-1GAXX
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| OCR Text |
...y and clocks on the ddr2 sdram. dmx, input data mask (x8 devices only): dm is an input mask signal for write data. input data is masked when dm is sampled high, along with that input data, during a write ac- cess. although dm pins are inpu... |
| Description |
256M X 72 DDR DRAM MODULE, DMA240 HALOGEN FREE, MO-237, UDIMM-240
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| File Size |
358.82K /
18 Page |
View
it Online |
Download Datasheet |
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