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Zarlink Semiconductor
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| Part No. |
ZL30409DDB
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| OCR Text |
..., c8, c16 , and c19 (sts-3/oc3 clock divided by 8) output clock signals ? provides 5 styles of 8 khz framing pulses ? holdover frequency a...synchronizer contains a digital phase-locked loop (dpll), which provides timing and synchronization ... |
| Description |
T1/E1 system synchronizer with stratum 3 holdover.
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| File Size |
293.30K /
32 Page |
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ZARLINK[Zarlink Semiconductor Inc]
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| Part No. |
ZL30409_DDB ZL30409 ZL30409_DDA
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| OCR Text |
...C6, C8, C16, and C19 (STS-3/OC3 clock divided by 8) output clock signals Provides 5 styles of 8 KHz framing pulses Holdover frequency accura...synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization ... |
| Description |
Dual reference frequency selectable, 3.3V Digital PLL with multiple clock outputs for T1/E1 and Stratum 4 and 4E applications, with Stratum 3 Holdover
T1/E1 System synchronizer with Stratum 3 Holdover
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| File Size |
284.56K /
32 Page |
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Download Datasheet |
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EXAR[Exar Corporation]
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| Part No. |
XRT94L43IB XRT94L43
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| OCR Text |
...rnal pointer leak algorithm for clock smoothing as well as to remove the jitter due to mapping and pointer movements. These De-synchronizer circuits do not need any external clock reference for its operation. The SONET/SDH transmit blocks a... |
| Description |
SONET/SDH STS-12/STM-4 to E3/DS3/STS-1 Mapper/Demapper
SONET/SDH STS-12/STM-4 TO E3/DS3/STS-1 MAPPER/DEMAPPER
From old datasheet system
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| File Size |
179.75K /
7 Page |
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Zarlink
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| Part No. |
MT9041B
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| OCR Text |
..., C2, C3, C4, C8 and C16 output clock signals Provides 3 different styles of 8 KHz framing pulses Attenuates wander from 1.9 Hz
DS5059 ISSU...synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization ... |
| Description |
T1/E1 System synchronizer
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| File Size |
512.83K /
21 Page |
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it Online |
Download Datasheet |
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ZARLINK[Zarlink Semiconductor Inc]
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| Part No. |
MT9046AN MT9046
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| OCR Text |
...C6, C8, C16, and C19 (STS-3/OC3 clock divided by 8) output clock signals Provides 5 styles of 8 KHz framing pulses Holdover frequency accura...synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization ... |
| Description |
T1/E1 System synchronizer with Holdover
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| File Size |
300.45K /
34 Page |
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it Online |
Download Datasheet |
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Price and Availability
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