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| Part No. |
CY2SSTU877BVXC-32T
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| OCR Text |
... of 1.8v, an av dd of 1.8v and sstl18 differential data input and output levels. this device is a zero delay buffer that distributes a differential clock input pair (ck, ck#) to ten differ- ential pair of clock outputs (y[0:9], y#[0:9]) a... |
| Description |
SSTU SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52
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| File Size |
127.85K /
8 Page |
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it Online |
Download Datasheet
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HYNIX SEMICONDUCTOR INC
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| Part No. |
HYMP512U64CP8-S6
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| OCR Text |
...ef supply reference voltage for sstl18 inputs v ddq supply power supplies for the ddr2 sdram output buf fers to provide improved noise immunity. for all current ddr2 unbuffered dimm designs, v ddq shares the same power plane as v dd pin... |
| Description |
128M X 64 DDR DRAM MODULE, 0.4 ns, ZMA240
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| File Size |
571.57K /
30 Page |
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it Online |
Download Datasheet |
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Nanya Technology Corpor...
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| Part No. |
NT5TU32M16FG NT5TU32M16FG-AC
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| OCR Text |
...ower (v dd , v ddq ) u = sstl18 (1.8v, 1.8v) organization (depth, width) 512mb = 32m16 = 64m8 m=mono device version f = 6 th version be n t 5t e f 32m16 u nanya component part numbering guide... |
| Description |
Commercial and Industrial DDR2 512Mb SDRAM
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| File Size |
3,694.79K /
107 Page |
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it Online |
Download Datasheet |
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Price and Availability
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