| |
|
 |
SAMSUNG SEMICONDUCTOR CO. LTD.
|
| Part No. |
KM736V799
|
| OCR Text |
...tion of oe , lbo and zz) are sampled on rising clock edges. the start and duration of the burst access is controlled by adsc , adsp and adv and chip select pins. the accesses are enabled with the chip select signals and output enab... |
| Description |
128Kx36-Bit Synchronous Pipelined Burst SRAM(128Kx36浣??姝ユ?姘寸嚎??????RAM)
|
| File Size |
404.13K /
17 Page |
 View
it Online |
Download Datasheet
|
| |
|
|
Nanya Techology
|
| Part No. |
NT5DS32M8BW
|
| OCR Text |
...s and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck . output (read) data is refer- enced to the crossings of ck and ck (both directions of crossing). cke, cke0, cke1 input clock ena... |
| Description |
(NT5DSxxMxBx) 256Mb DDR SDRAM
|
| File Size |
1,959.62K /
80 Page |
View
it Online |
Download Datasheet |
| |
|
|
|
| Part No. |
MT41K256M4JP-125G
|
| OCR Text |
...ray in the respective bank. a10 sampled during a precharge com- mand determines whether the precharge applies to one bank (a10 low, bank selected by ba[2:0]) or all banks (a10 high). the address inputs also provide the op-code during a load... |
| Description |
256M X 4 DDR DRAM, PBGA78
|
| File Size |
446.14K /
21 Page |
View
it Online |
Download Datasheet |
| |
|
|
|
| Part No. |
KM736V799T-55 KM736V799T-50
|
| OCR Text |
...tion of oe , lbo and zz) are sampled on rising clock edges. the start and duration of the burst access is controlled by adsc , adsp and adv and chip select pins. the accesses are enabled with the chip select signals and output enab... |
| Description |
128K X 36 CACHE SRAM, 3.1 ns, PQFP100
|
| File Size |
408.77K /
15 Page |
View
it Online |
Download Datasheet |
| |
|
|
HYNIX SEMICONDUCTOR INC
|
| Part No. |
HMT41GS6MFR8C-RD
|
| OCR Text |
...s , cas , we in active low when sampled at the cross point of the rising edge of ck, signals cas , ras , and we define the operation to be executed by the sdram. v refdq v refca supply reference voltage for sstl15 inputs. ba[2:0] in ? sel... |
| Description |
DDR DRAM MODULE, DMA204
|
| File Size |
345.31K /
48 Page |
View
it Online |
Download Datasheet |
| |
|
|
|
| Part No. |
K4T51163QE-ZPD50
|
| OCR Text |
... and cont rol input signals are sampled on the crossing of the positive edge of ck and negative edge of ck . output (read) data is referenced to the crossings of ck and ck (both directions of crossing). cke input clock enable: cke high ac... |
| Description |
32M X 16 DDR DRAM, 0.5 ns, PBGA84
|
| File Size |
449.51K /
25 Page |
View
it Online |
Download Datasheet |
| |
|
|
Nanya Techology
|
| Part No. |
NT5DS32M8BF NT5DS64M4BT
|
| OCR Text |
...s and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck . output (read) data is refer- enced to the crossings of ck and ck (both directions of crossing). cke, cke0, cke1 input clock ena... |
| Description |
(NT5DSxxMxBx) 256Mb DDR SDRAM
|
| File Size |
1,953.01K /
80 Page |
View
it Online |
Download Datasheet |
| |
|
|
|
| Part No. |
K7A803601A-TC11
|
| OCR Text |
...tion of oe , lbo and zz) are sampled on rising clock edges. the start and duration of the burst access is controlled by adsc , adsp and adv and chip select pins. the accesses are enabled with the chip select signals and output enab... |
| Description |
256K X 36 CACHE SRAM, 4.2 ns, PQFP100
|
| File Size |
468.30K /
17 Page |
View
it Online |
Download Datasheet |
|
Price and Availability
|
