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GSI Technology, Inc.
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| Part No. |
GS8180QV18D-200I GS8180QV18D-133I GS8180QV18D-100I
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| OCR Text |
... with the common i/o family of sigmarams, the sigmaquad family of srams allows a user to implement the interface protocol best suited to the task at hand. clocking and addr essing schemes a burst of 2 sigmaquad sram is a synchronous de... |
| Description |
18Mb Burst of 2 SigmaQuad SRAM 1M X 18 STANDARD SRAM, 2.3 ns, PBGA165
18Mb Burst of 2 SigmaQuad SRAM 1M X 18 STANDARD SRAM, 3 ns, PBGA165
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| File Size |
474.27K /
30 Page |
 View
it Online |
Download Datasheet
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GSI Technology, Inc.
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| Part No. |
GS815018AB-250 GS815018AGB-250 GS815036AB-250 GS815036AGB-250I GS815018AGB-357 GS815018AGB-333I GS815018AB-300I GS815036AB-300 GS815036AB-333I GS815036AGB-333I GS815036AB-333IT GS815018AB-357IT GS815036AB-357IT GS815018AB-250T
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| OCR Text |
...iver impedance control hstl i/o sigmarams are suppli ed with programmable impedan ce output drivers. the zq pin must be connected to v ss via an external resistor, rq, to allow the sram to monitor and adjust its output driver impedance. t... |
| Description |
1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM 1M X 18 LATE-WRITE SRAM, 2 ns, PBGA119
1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM 512K X 36 LATE-WRITE SRAM, 2 ns, PBGA119
1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM 1M X 18 LATE-WRITE SRAM, 1.4 ns, PBGA119
1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM 1M X 18 LATE-WRITE SRAM, 1.5 ns, PBGA119
1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM 1M X 18 LATE-WRITE SRAM, 1.6 ns, PBGA119
1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM 512K X 36 LATE-WRITE SRAM, 1.6 ns, PBGA119
1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM 512K X 36 LATE-WRITE SRAM, 1.5 ns, PBGA119
512K X 36 LATE-WRITE SRAM, 1.4 ns, PBGA119
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| File Size |
221.21K /
25 Page |
View
it Online |
Download Datasheet |
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GSI Technology, Inc.
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| Part No. |
GS8150V18AB-250 GS8150V36AB-250 GS8150V36AGB-250 GS8150V36AGB-250I GS8150V18AGB-300 GS8150V36AGB-333I GSITECHNOLOGY-GS8150V18AB-250T
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| OCR Text |
...iver impedance control hstl i/o sigmarams are suppli ed with programmable impedan ce output drivers. the zq pin must be connected to v ss via an external resistor, rq, to allow the sram to monitor and adjust its output driver impedance. t... |
| Description |
1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM 1M X 18 LATE-WRITE SRAM, 2 ns, PBGA119
1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM 512K X 36 LATE-WRITE SRAM, 2 ns, PBGA119
1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM 1M X 18 LATE-WRITE SRAM, 1.6 ns, PBGA119
1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM 512K X 36 LATE-WRITE SRAM, 1.5 ns, PBGA119
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| File Size |
218.81K /
25 Page |
View
it Online |
Download Datasheet |
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GSI Technology, Inc.
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| Part No. |
GS8180QV36D-133
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| OCR Text |
... with the common i/o family of sigmarams, the sigmaquad family of srams allows a user to implement the interface protocol best suited to the task at hand. clocking and addr essing schemes a burst of 2 sigmaquad sram is a synchronous de... |
| Description |
18Mb Burst of 2 SigmaQuad SRAM 512K X 36 STANDARD SRAM, 3 ns, PBGA165
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| File Size |
540.77K /
30 Page |
View
it Online |
Download Datasheet |
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GSI Technology, Inc.
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| Part No. |
GS8180D18D-100I GS8180D18D-167
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| OCR Text |
... with the common i/o family of sigmarams, the sigmaquad family of srams allows a user to implement the interface protocol best suited to the task at hand. clocking and addr essing schemes a burst of 4 sigmaquad sram is a synchronous... |
| Description |
18Mb Burst of 4 SigmaQuad SRAM 1M X 18 STANDARD SRAM, 3 ns, PBGA165
18Mb Burst of 4 SigmaQuad SRAM 1M X 18 STANDARD SRAM, 2.5 ns, PBGA165
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| File Size |
666.34K /
28 Page |
View
it Online |
Download Datasheet |
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GSI Technology, Inc.
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| Part No. |
GS818QV18D-200I GS818QV36D-200T GS818QV36D-200I GS818QV36D-200IT GS818QV18D-200T GS818QV18D-200IT
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| OCR Text |
... with the common i/o family of sigmarams, the sigmaquad family of srams allows a user to implement the in terface protocol best suited to the task at hand. clocking and addr essing schemes a 2x2b2sigmaquad sram is a synchronous devic... |
| Description |
1M X 18 STANDARD SRAM, 2.3 ns, PBGA165 13 X 15 MM, 1 MM PITCH, MO-216CAB-1, BGA-165
512K X 36 STANDARD SRAM, 2.3 ns, PBGA165 13 X 15 MM, 1 MM PITCH, MO-216CAB-1, BGA-165
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| File Size |
500.46K /
29 Page |
View
it Online |
Download Datasheet |
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