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renesas Electronics Corporation.r>renesas Electronics, Corp.r>
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Part No. |
M3r='#FF0000'>8030F2L-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xHP M3r='#FF0000'>8030F2L-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xr='#FF0000'>kP M3r='#FF0000'>8030F2L-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xSP M3r='#FF0000'>8030F2L-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xWG M3r='#FF0000'>8030MAL-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xWG M3r='#FF0000'>8030MAL-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xr='#FF0000'>kP M3r='#FF0000'>8030FAL-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xSP M3r='#FF0000'>8031FAL-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xHP M3r='#FF0000'>8030FAL-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xWG M3r='#FF0000'>8030MAL-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xHP M3r='#FF0000'>8030FAL-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xr='#FF0000'>kP M3r='#FF0000'>8031FAL-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xr='#FF0000'>kP M3r='#FF0000'>8030FAL-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xHP M3r='#FF0000'>8031FAL-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xSP M3r='#FF0000'>8031FAL-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xWG M3r='#FF0000'>8030MAL-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xSP M3r='#FF0000'>8030F3L-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xHP M3r='#FF0000'>8030F3L-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xWG M3r='#FF0000'>8030M3L-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xr='#FF0000'>kP M3r='#FF0000'>8030F3L-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xSP M3r='#FF0000'>8030F3L-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xr='#FF0000'>kP M3r='#FF0000'>8030M3L-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xHP M3r='#FF0000'>8030FBL-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xWG M3r='#FF0000'>8030MBL-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xHP M3r='#FF0000'>8030FBL-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xHP M3r='#FF0000'>8030FBL-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xSP M3r='#FF0000'>8030MBL-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xr='#FF0000'>kP M3r='#FF0000'>8030M2L-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xHP M3r='#FF0000'>8030M2L-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xr='#FF0000'>kP M3r='#FF0000'>8030M2L-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xSP M3r='#FF0000'>8030M2L-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xWG M3r='#FF0000'>8031F2L-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xHP M3r='#FF0000'>8031F2L-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xr='#FF0000'>kP M3r='#FF0000'>8031F2L-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xSP M3r='#FF0000'>8031F2L-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xWG M3r='#FF0000'>8030FB-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xHP M3r='#FF0000'>8031FBL-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xSP M3r='#FF0000'>8035MBL-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xSP M3r='#FF0000'>803r='#FF0000'>8FBL-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xSP M3r='#FF0000'>8039FBL-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xSP M3r='#FF0000'>8030MBL-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xSP M3r='#FF0000'>8036MBL-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xSP M3r='#FF0000'>8037FBL-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xSP M3r='#FF0000'>8037MBL-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xSP M3r='#FF0000'>8036FBL-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xSP M3r='#FF0000'>803r='#FF0000'>8MBL-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xSP M3r='#FF0000'>8031FC-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xHP M3r='#FF0000'>8031FC-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xr='#FF0000'>kP M3r='#FF0000'>8031FC-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xWG M3r='#FF0000'>8031FCL-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xHP M3r='#FF0000'>8031FCL-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xr='#FF0000'>kP M3r='#FF0000'>8031FCL-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xSP M3r='#FF0000'>8031FCL-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xWG M3r='#FF0000'>8031F5-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xr='#FF0000'>kP M3r='#FF0000'>8031F5-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xSP M3r='#FF0000'>8031F5-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xWG M3r='#FF0000'>8031F5L-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xHP M3r='#FF0000'>8031F5L-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xr='#FF0000'>kP M3r='#FF0000'>8031F5L-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xSP M3r='#FF0000'>8031F5L-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xWG M3r='#FF0000'>8030F1-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xHP M3r='#FF0000'>8030F1-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xr='#FF0000'>kP M3r='#FF0000'>8030F1-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xSP M3r='#FF0000'>8030F1-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xWG M3r='#FF0000'>8030F1L-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xHP M3r='#FF0000'>8030F1L-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xr='#FF0000'>kP M3r='#FF0000'>8030F1L-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xSP M3r='#FF0000'>8030F1L-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xWG M3r='#FF0000'>8031F1-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xr='#FF0000'>kP M3r='#FF0000'>8031F1-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xWG M3r='#FF0000'>8031F1L-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xHP M3r='#FF0000'>8031F1L-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xr='#FF0000'>kP M3r='#FF0000'>8031F6-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xHP M3r='#FF0000'>8031F6-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xr='#FF0000'>kP M3r='#FF0000'>8031F6-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xSP M3r='#FF0000'>8031F6-r='#FF0000'>xr='#FF0000'>xr='#FF0000'>xWG M
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Description |
r='#FF0000'>256 r='#FF0000'>kbit (32r='#FF0000'>k r='#FF0000'>x r='#FF0000'>8) nvSrAM; Organization: 32r='#FF0000'>kb r='#FF0000'>x r='#FF0000'>8; Vcc (V): 2.7 to 3.6 V; Density: r='#FF0000'>256 r='#FF0000'>kb; Pacr='#FF0000'>kage: SOICr>3.3V Zero Delay Clocr='#FF0000'>k Buffer; Voltage (V): 3.3 V; Frequency range: 10 MHz to 133 MHz; Outputs: 5; Operating range: 0 to 70 Cr>r='#FF0000'>256r='#FF0000'>k (32r='#FF0000'>k r='#FF0000'>x r='#FF0000'>8) r='#FF0000'>static rAM; Density: r='#FF0000'>256 r='#FF0000'>kb; Organization: 32r='#FF0000'>kb r='#FF0000'>x r='#FF0000'>8; Vcc (V): 4.50 to 5.50 V;r>Three-PLL General Purpose FLASH Programmable Clocr='#FF0000'>k Generator; Voltage (V): 3.3 V; Input range: 1 MHz to 166 MHz; Output range: 1 MHz to 200 MHz; Outputs: 6r>5V, 3.3V, ISr(TM) High-Performance CPLDs; # Macrocells: r='#FF0000'>256; Vcc (V): 3.3; fMar='#FF0000'>x (MHz): 66; tPD (ns): 12r>r='#FF0000'>8-Mbit (512r='#FF0000'>k r='#FF0000'>x 16) r='#FF0000'>static rAM; Density: r='#FF0000'>8 Mb; Organization: 512r='#FF0000'>kb r='#FF0000'>x 16; Vcc (V): 2.20 to 3.60 V;r>9-Mbit (r='#FF0000'>256r='#FF0000'>k r='#FF0000'>x 36/512r='#FF0000'>k r='#FF0000'>x 1r='#FF0000'>8) Pipelined SrAM; Architecture: Standard Sync, Pipeline SCD; Density: 9 Mb; Organization: 512r='#FF0000'>kb r='#FF0000'>x 1r='#FF0000'>8; Vcc (V): 3.1 to 3.6 Vr>9-Mbit (r='#FF0000'>256r='#FF0000'>k r='#FF0000'>x 36/512r='#FF0000'>k r='#FF0000'>x 1r='#FF0000'>8) Flow-Through SrAM; Architecture: Standard Sync, Flow-through; Density: 9 Mb; Organization: 512r='#FF0000'>kb r='#FF0000'>x 1r='#FF0000'>8; Vcc (V): 3.1 to 3.6 Vr>1r='#FF0000'>8-Mbit QDr(TM)-II SrAM 4-Word Burst Architecture; Architecture: QDr-II, 4 Word Burst; Density: 1r='#FF0000'>8 Mb; Organization: 512r='#FF0000'>kb r='#FF0000'>x 36; Vcc (V): 1.7 to 1.9 Vr>Four Output PCI-r='#FF0000'>x and General Purpose Buffer; Voltage (V): 3.3 V; Frequency range: 0 MHz to 140 MHz; Outputs: 4; Operating range: 0 to 70 Cr>1r='#FF0000'>8-Mbit QDr(TM)-II SrAM 2-Word Burst Architecture; Architecture: QDr-II, 2 Word Burst; Density: 1r='#FF0000'>8 Mb; Organization: 512r='#FF0000'>kb r='#FF0000'>x 36; Vcc (V): 1.7 to 1.9 Vr>9-Mbit (r='#FF0000'>256r='#FF0000'>k r='#FF0000'>x 36/512r='#FF0000'>k r='#FF0000'>x 1r='#FF0000'>8) Flow-Through SrAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 9 Mb; Organization: 512r='#FF0000'>kb r='#FF0000'>x 1r='#FF0000'>8; Vcc (V): 3.1 to 3.6 Vr>9-Mbit (r='#FF0000'>256r='#FF0000'>k r='#FF0000'>x 36/512r='#FF0000'>k r='#FF0000'>x 1r='#FF0000'>8) Pipelined SrAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 9 Mb; Organization: 512r='#FF0000'>kb r='#FF0000'>x 1r='#FF0000'>8; Vcc (V): 2.4 to 2.6 Vr>4-Mbit (512r='#FF0000'>k r='#FF0000'>x r='#FF0000'>8) r='#FF0000'>static rAM; Density: 4 Mb; Organization: 512r='#FF0000'>kb r='#FF0000'>x r='#FF0000'>8; Vcc (V): 4.50 to 5.50 V;r>4-Mbit (r='#FF0000'>256r='#FF0000'>k r='#FF0000'>x 16) r='#FF0000'>static rAM; Density: 4 Mb; Organization: r='#FF0000'>256r='#FF0000'>kb r='#FF0000'>x 16; Vcc (V): 2.20 to 3.60 V;r>64r='#FF0000'>k r='#FF0000'>x 16 r='#FF0000'>static rAM; Density: 1 Mb; Organization: 64r='#FF0000'>kb r='#FF0000'>x 16; Vcc (V): 3.0 to 3.6 V;r>1-Mbit (64r='#FF0000'>k r='#FF0000'>x 16) r='#FF0000'>static rAM; Density: 1 Mb; Organization: 64r='#FF0000'>kb r='#FF0000'>x 16; Vcc (V): 4.5 to 5.5 V;r>9-Mbit (r='#FF0000'>256r='#FF0000'>k r='#FF0000'>x 36/512r='#FF0000'>k r='#FF0000'>x 1r='#FF0000'>8) Pipelined SrAM; Architecture: Standard Sync, Pipeline SCD; Density: 9 Mb; Organization: r='#FF0000'>256r='#FF0000'>kb r='#FF0000'>x 36; Vcc (V): 3.1 to 3.6 Vr>1-Mbit (64r='#FF0000'>k r='#FF0000'>x 16) r='#FF0000'>static rAM; Density: 1 Mb; Organization: 64r='#FF0000'>kb r='#FF0000'>x 16; Vcc (V): 3.0 to 3.6 V;r>4 Mbit (512r='#FF0000'>k r='#FF0000'>x r='#FF0000'>8/r='#FF0000'>256r='#FF0000'>k r='#FF0000'>x 16) nvSrAM; Organization: 512r='#FF0000'>kb r='#FF0000'>x r='#FF0000'>8; Vcc (V): 2.7 to 3.6 V; Density: 4 Mb; Pacr='#FF0000'>kage: TSOPr>4 Mbit (512r='#FF0000'>k r='#FF0000'>x r='#FF0000'>8/r='#FF0000'>256r='#FF0000'>k r='#FF0000'>x 16) nvSrAM; Organization: r='#FF0000'>256r='#FF0000'>kb r='#FF0000'>x 16; Vcc (V): 2.7 to 3.6 V; Density: 4 Mb; Pacr='#FF0000'>kage: TSOPr>16-Mbit (1M r='#FF0000'>x 16 / 2M r='#FF0000'>x r='#FF0000'>8) r='#FF0000'>static rAM; Density: 16 Mb; Organization: 1Mb r='#FF0000'>x 16; Vcc (V): 4.50 to 5.50 V;r>4r='#FF0000'>k r='#FF0000'>x 16/1r='#FF0000'>8 and r='#FF0000'>8r='#FF0000'>k r='#FF0000'>x 16/1r='#FF0000'>8 Dual-Port r='#FF0000'>static rAM with SEM, INT, BUSY; Density: 12r='#FF0000'>8 r='#FF0000'>kb; Organization: r='#FF0000'>8r='#FF0000'>kb r='#FF0000'>x 16; Vcc (V): 4.5 to 5.5 V; Speed: 35 nsr>9-Mbit (r='#FF0000'>256r='#FF0000'>k r='#FF0000'>x 36/512r='#FF0000'>k r='#FF0000'>x 1r='#FF0000'>8) Pipelined SrAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 9 Mb; Organization: r='#FF0000'>256r='#FF0000'>kb r='#FF0000'>x 36; Vcc (V): 3.1 to 3.6 Vr>9-Mbit (r='#FF0000'>256r='#FF0000'>k r='#FF0000'>x 36/512r='#FF0000'>k r='#FF0000'>x 1r='#FF0000'>8) Flow-Through SrAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 9 Mb; Organization: r='#FF0000'>256r='#FF0000'>kb r='#FF0000'>x 36; Vcc (V): 3.1 to 3.6 Vr>9-Mbit (r='#FF0000'>256r='#FF0000'>k r='#FF0000'>x 36/512r='#FF0000'>k r='#FF0000'>x 1r='#FF0000'>8) Pipelined SrAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 9 Mb; Organization: r='#FF0000'>256r='#FF0000'>kb r='#FF0000'>x 36; Vcc (V): 2.4 to 2.6 Vr>9-Mbit (r='#FF0000'>256r='#FF0000'>k r='#FF0000'>x 36/512r='#FF0000'>k r='#FF0000'>x 1r='#FF0000'>8) Pipelined SrAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 9 Mb; Organization: 512r='#FF0000'>kb r='#FF0000'>x 1r='#FF0000'>8; Vcc (V): 3.1 to 3.6 Vr>r='#FF0000'>8-Mbit (512r='#FF0000'>k r='#FF0000'>x 16) r='#FF0000'>static rAM; Density: r='#FF0000'>8 Mb; Organization: 512r='#FF0000'>kb r='#FF0000'>x 16; Vcc (V): 4.50 to 5.50 V;r>9-Mbit (r='#FF0000'>256r='#FF0000'>k r='#FF0000'>x 36/512r='#FF0000'>k r='#FF0000'>x 1r='#FF0000'>8) Flow-Through SrAM; Architecture: Standard Sync, Flow-through; Density: 9 Mb; Organization: r='#FF0000'>256r='#FF0000'>kb r='#FF0000'>x 36; Vcc (V): 3.1 to 3.6 Vr>r='#FF0000'>256r='#FF0000'>k r='#FF0000'>x 16 r='#FF0000'>static rAM; Density: 4 Mb; Organization: r='#FF0000'>256r='#FF0000'>kb r='#FF0000'>x 16; Vcc (V): 4.5 to 5.5 V;r>9-Mbit (r='#FF0000'>256r='#FF0000'>k r='#FF0000'>x 36/512r='#FF0000'>k r='#FF0000'>x 1r='#FF0000'>8) Pipelined DCD Sync SrAM; Architecture: Standard Sync, Pipeline DCD; Density: 9 Mb; Organization: r='#FF0000'>256r='#FF0000'>kb r='#FF0000'>x 36; Vcc (V): 3.1 to 3.6 Vr>4-Mbit (r='#FF0000'>256r='#FF0000'>k r='#FF0000'>x 16) r='#FF0000'>static rAM; Density: 4 Mb; Organization: r='#FF0000'>256r='#FF0000'>kb r='#FF0000'>x 16; Vcc (V): 3.0 to 3.6 V;r>r='#FF0000'>8-Mbit (1024r='#FF0000'>k r='#FF0000'>x r='#FF0000'>8) r='#FF0000'>static rAM; Density: r='#FF0000'>8 Mb; Organization: 1Mb r='#FF0000'>x r='#FF0000'>8; Vcc (V): 2.20 to 3.60 V;r>1r='#FF0000'>8-Mbit (512r='#FF0000'>k r='#FF0000'>x 36/1M r='#FF0000'>x 1r='#FF0000'>8) Pipelined SrAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 1r='#FF0000'>8 Mb; Organization: 512r='#FF0000'>kb r='#FF0000'>x 36; Vcc (V): 3.1 to 3.6 Vr>r='#FF0000'>256r='#FF0000'>k r='#FF0000'>x 16 r='#FF0000'>static rAM; Density: 4 Mb; Organization: r='#FF0000'>256r='#FF0000'>kb r='#FF0000'>x 16; Vcc (V): 3.0 to 3.6 V;r>r='#FF0000'>8-Mbit (1M r='#FF0000'>x r='#FF0000'>8) r='#FF0000'>static rAM; Density: r='#FF0000'>8 Mb; Organization: 1Mb r='#FF0000'>x r='#FF0000'>8; Vcc (V): 2.20 to 3.60 V;r>3.3V Zero Delay Buffer; Voltage (V): 3.3 V; Frequency range: 10 MHz to 133 MHz; Outputs: r='#FF0000'>8; Operating range: -40 to r='#FF0000'>85 Cr>Programmable Sr='#FF0000'>kew Clocr='#FF0000'>k Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to r='#FF0000'>80 MHz; Outputs: r='#FF0000'>8; Operating range: -40 to r='#FF0000'>85 Cr>1r='#FF0000'>8-Mbit (512r='#FF0000'>k r='#FF0000'>x 36/1M r='#FF0000'>x 1r='#FF0000'>8) Flow-Through SrAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 1r='#FF0000'>8 Mb; Organization: 512r='#FF0000'>kb r='#FF0000'>x 36; Vcc (V): 3.1 to 3.6 Vr>1r='#FF0000'>8-Mbit (512r='#FF0000'>k r='#FF0000'>x 36/1M r='#FF0000'>x 1r='#FF0000'>8) Pipelined SrAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 1r='#FF0000'>8 Mb; Organization: 1Mb r='#FF0000'>x 1r='#FF0000'>8; Vcc (V): 3.1 to 3.6 Vr>512r='#FF0000'>k r='#FF0000'>x r='#FF0000'>8 r='#FF0000'>static rAM; Density: 4 Mb; Organization: 512r='#FF0000'>kb r='#FF0000'>x r='#FF0000'>8; Vcc (V): 4.5 to 5.5 V;r>1r='#FF0000'>8-Mbit (512r='#FF0000'>k r='#FF0000'>x 36/1M r='#FF0000'>x 1r='#FF0000'>8) Pipelined SrAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 1r='#FF0000'>8 Mb; Organization: 512r='#FF0000'>kb r='#FF0000'>x 36; Vcc (V): 2.4 to 2.6 Vr>2.5V or 3.3V, 200-MHz, 1:12 Clocr='#FF0000'>k Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency range: 0 MHz to 200 MHz; Outputs: 12; Operating range: -40 to r='#FF0000'>85 Cr>3.3V Zero Delay Clocr='#FF0000'>k Buffer; Voltage (V): 3.3 V; Frequency range: 10 MHz to 133 MHz; Outputs: 5; Operating range: -40 to r='#FF0000'>85 Cr>2M r='#FF0000'>x r='#FF0000'>8 r='#FF0000'>static rAM; Density: 16 Mb; Organization: 2Mb r='#FF0000'>x r='#FF0000'>8; Vcc (V): 3.0 to 3.6 V;r>16 Mbit (512r='#FF0000'>k r='#FF0000'>x 32) r='#FF0000'>static rAM; Density: 16 Mb; Organization: 512r='#FF0000'>kb r='#FF0000'>x 32; Vcc (V): 3.0 to 3.6 V;r>3.3V Zero Delay Buffer; Voltage (V): 3.3 V; Frequency range: 10 MHz to 133 MHz; Outputs: r='#FF0000'>8; Operating range: 0 to 70 Cr>r='#FF0000'>8-Mbit (1M r='#FF0000'>x r='#FF0000'>8) r='#FF0000'>static rAM; Density: r='#FF0000'>8 Mb; Organization: 1Mb r='#FF0000'>x r='#FF0000'>8; Vcc (V): 3.0 to 3.6 V;r>5V, 3.3V, ISr(TM) High-Performance CPLDs; # Macrocells: 64; Vcc (V): 5; fMar='#FF0000'>x (MHz): 125; tPD (ns): 6r>r='#FF0000'>2-mbit (12r='#FF0000'>8r='#FF0000'>k r='#FF0000'>x 16) r='#FF0000'>static rAM; Density: 2 Mb; Organization: 12r='#FF0000'>8r='#FF0000'>kb r='#FF0000'>x 16; Vcc (V): 3.0 to 3.6 V;r>16-Mbit (1M r='#FF0000'>x 16) r='#FF0000'>static rAM; Density: 16 Mb; Organization: 1Mb r='#FF0000'>x 16; Vcc (V): 3.0 to 3.6 V;r>4-Mbit (r='#FF0000'>256r='#FF0000'>k r='#FF0000'>x 1r='#FF0000'>8) Pipelined DCD Sync SrAM; Architecture: Standard Sync, Pipeline DCD; Density: 4 Mb; Organization: r='#FF0000'>256r='#FF0000'>kb r='#FF0000'>x 1r='#FF0000'>8; Vcc (V): 3.1 to 3.6 Vr>512r='#FF0000'>k (32r='#FF0000'>k r='#FF0000'>x 16) r='#FF0000'>static rAM; Density: 512 r='#FF0000'>kb; Organization: 32r='#FF0000'>kb r='#FF0000'>x 16; Vcc (V): 3.0 to 3.6 V;r>4-Mbit (12r='#FF0000'>8r='#FF0000'>k r='#FF0000'>x 36) Pipelined SrAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 4 Mb; Organization: 12r='#FF0000'>8r='#FF0000'>kb r='#FF0000'>x 36; Vcc (V): 3.1 to 3.6 Vr>1M r='#FF0000'>x 16 r='#FF0000'>static rAM; Density: 16 Mb; Organization: 1Mb r='#FF0000'>x 16; Vcc (V): 3.0 to 3.6 V;r>Programmable Sr='#FF0000'>kew Clocr='#FF0000'>k Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to r='#FF0000'>80 MHz; Outputs: r='#FF0000'>8; Operating range: 0 to 70 Cr>3.3V Zero Delay Clocr='#FF0000'>k Buffer; Voltage (V): 3.3 V; Frequency range: 10 MHz to 133 MHz; Outputs: 9; Operating range: 0 to 70 Cr>r='#FF0000'>mobl(r) 2 Mbit (12r='#FF0000'>8r='#FF0000'>k r='#FF0000'>x 16) r='#FF0000'>static rAM; Density: 2 Mb; Organization: 12r='#FF0000'>8r='#FF0000'>kb r='#FF0000'>x 16; Vcc (V): 2.20 to 3.60 V;r>rambus(r) r='#FF0000'>xDr(TM) Clocr='#FF0000'>k Generator; VDD: 2.5 V; Input Frequency: 100 MHz to 133 MHz; Output Frequency: 300 MHz to r='#FF0000'>800 MHz; # Out: 4r>r='#FF0000'>2-mbit (12r='#FF0000'>8r='#FF0000'>k r='#FF0000'>x 16) r='#FF0000'>static rAM; Density: 2 Mb; Organization: 12r='#FF0000'>8r='#FF0000'>kb r='#FF0000'>x 16; Vcc (V): 2.20 to 3.60 V;r>4-Mbit (12r='#FF0000'>8r='#FF0000'>k r='#FF0000'>x 36) Pipelined Sync SrAM; Architecture: Standard Sync, Pipeline SCD; Density: 4 Mb; Organization: 12r='#FF0000'>8r='#FF0000'>kb r='#FF0000'>x 36; Vcc (V): 3.1 to 3.6 Vr>5V, 3.3V, ISr(TM) High-Performance CPLDs; # Macrocells: 12r='#FF0000'>8; Vcc (V): 5; fMar='#FF0000'>x (MHz): 167; tPD (ns): 7r>2.5V or 3.3V, 200-MHz, 1:10 Clocr='#FF0000'>k Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency range: 0 MHz to 200 MHz; Outputs: 10; Operating range: 0 to 70 Cr>5V, 3.3V, ISr(TM) High-Performance CPLDs; # Macrocells: 12r='#FF0000'>8; Vcc (V): 5; fMar='#FF0000'>x (MHz): 100; tPD (ns): 7r>5V, 3.3V, ISr(TM) High-Performance CPLDs; # Macrocells: 12r='#FF0000'>8; Vcc (V): 5; fMar='#FF0000'>x (MHz): 125; tPD (ns): 7r>1r='#FF0000'>8-Mbit DDr-II SrAM 2-Word Burst Architecture; Architecture: DDr-II CIO, 2 Word Burst; Density: 1r='#FF0000'>8 Mb; Organization: 512r='#FF0000'>kb r='#FF0000'>x 36; Vcc (V): 1.7 to 1.9 Vr>Low Voltage Programmable Sr='#FF0000'>kew Clocr='#FF0000'>k Buffer; Voltage (V): 3.3 V; Operating Frequency: 3.75 MHz to r='#FF0000'>80 MHz; Outputs: r='#FF0000'>8; Operating range: 0 to 70 Cr>Spread Spectrum Clocr='#FF0000'>k Generator; Voltage(V): 3.3 V; Input Frequency range: 25 MHz to 100 MHz; Output Frequency range: 25 MHz to 100 MHz; Operating range: 0 to 70 C; Pacr='#FF0000'>kage: SOICr>Low Sr='#FF0000'>kew Clocr='#FF0000'>k Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to r='#FF0000'>80 MHz; Outputs: r='#FF0000'>8; Operating range: 0 to 70 Cr>5V, 3.3V, ISr(TM) High-Performance CPLDs; # Macrocells: 64; Vcc (V): 3.3; fMar='#FF0000'>x (MHz): 143; tPD (ns): 9 单芯位CMOS微机r>5V, 3.3V, ISr(TM) High-Performance CPLDs; # Macrocells: 64; Vcc (V): 5; fMar='#FF0000'>x (MHz): 154; tPD (ns): 6 单芯位CMOS微机r>SINGLE-CHIP r='#FF0000'>8-BIT CMOS MICrOCOMPUTEr 单芯位CMOS微机r>5V, 3.3V, ISr(TM) High-Performance CPLDs; # Macrocells: 64; Vcc (V): 3.3; fMar='#FF0000'>x (MHz): 100; tPD (ns): 9 单芯位CMOS微机r>5V, 3.3V, ISr(TM) High-Performance CPLDs; # Macrocells: 12r='#FF0000'>8; Vcc (V): 3.3; fMar='#FF0000'>x (MHz): r='#FF0000'>83; tPD (ns): 10 单芯位CMOS微机r>5V, 3.3V, ISr(TM) High-Performance CPLDs; # Macrocells: 64; Vcc (V): 5; fMar='#FF0000'>x (MHz): 125; tPD (ns): 6 单芯位CMOS微机r>Three-PLL General-Purpose EPrOM Programmable Clocr='#FF0000'>k Generator; Voltage (V): 3.3/5.0 V; Input range: 1 MHz to 30 MHz; Output range: .077 MHz to 100 MHz; Outputs: 6 单芯位CMOS微机r>r='#FF0000'>8-Mbit (512r='#FF0000'>k r='#FF0000'>x 16) r='#FF0000'>mobl(r) r='#FF0000'>static rAM; Density: r='#FF0000'>8 Mb; Organization: 512r='#FF0000'>kb r='#FF0000'>x 16; Vcc (V): 2.20 to 3.60 V; 单芯位CMOS微机r>High Speed Low Voltage Programmable Sr='#FF0000'>kew Clocr='#FF0000'>k Buffer; Voltage (V): 3.3 V; Operating Frequency: 3.75 MHz to 110 MHz; Outputs: r='#FF0000'>8; Operating range: 0 to 70 C 单芯位CMOS微机r>3.3V SDrAM Buffer for Mobile PCs with 4 SO-DIMMs; Voltage (V): 3.3 V; Frequency range: 0 MHz to 100 MHz; Outputs: 10; Operating range: 0 to 70 C 单芯位CMOS微机r>3.3V Zero Delay Clocr='#FF0000'>k Buffer; Voltage (V): 3.3 V; Frequency range: 10 MHz to 133 MHz; Outputs: 9; Operating range: -40 to r='#FF0000'>85 C 单芯位CMOS微机r>Programmable Sr='#FF0000'>kew Clocr='#FF0000'>k Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to r='#FF0000'>80 MHz; Outputs: r='#FF0000'>8; Operating range: -40 to r='#FF0000'>85 C 单芯位CMOS微机r>r='#FF0000'>2-mbit (12r='#FF0000'>8r='#FF0000'>k r='#FF0000'>x 16) r='#FF0000'>static rAM; Density: 2 Mb; Organization: 12r='#FF0000'>8r='#FF0000'>kb r='#FF0000'>x 16; Vcc (V): 3.0 to 3.6 V; 单芯位CMOS微机r>r='#FF0000'>mobl(r) 1 Mbit (12r='#FF0000'>8r='#FF0000'>k r='#FF0000'>x r='#FF0000'>8) r='#FF0000'>static rAM; Density: 1 Mb; Organization: 12r='#FF0000'>8r='#FF0000'>kb r='#FF0000'>x r='#FF0000'>8; Vcc (V): 2.20 to 3.60 V; 单芯位CMOS微机r>1r='#FF0000'>8-Mbit QDr(TM)-II SrAM 2-Word Burst Architecture; Architecture: QDr-II, 2 Word Burst; Density: 1r='#FF0000'>8 Mb; Organization: 1Mb r='#FF0000'>x 1r='#FF0000'>8; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机r>1-Mbit (12r='#FF0000'>8r='#FF0000'>k r='#FF0000'>x r='#FF0000'>8) r='#FF0000'>static rAM; Density: 1 Mb; Organization: 12r='#FF0000'>8r='#FF0000'>kb r='#FF0000'>x r='#FF0000'>8; Vcc (V): 4.50 to 5.50 V; 单芯位CMOS微机r>4-Mbit (r='#FF0000'>256r='#FF0000'>k r='#FF0000'>x 1r='#FF0000'>8) Pipelined Sync SrAM; Architecture: Standard Sync, Pipeline SCD; Density: 4 Mb; Organization: r='#FF0000'>256r='#FF0000'>kb r='#FF0000'>x 1r='#FF0000'>8; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机r>r='#FF0000'>2-mbit (64r='#FF0000'>k r='#FF0000'>x 32) Pipelined Sync SrAM; Architecture: Standard Sync, Pipeline SCD; Density: 2 Mb; Organization: 64r='#FF0000'>kb r='#FF0000'>x 32; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机r>200-MHz Field Programmable Zero Delay Buffer; Voltage (V): 2.5/3.3 V; Frequency range: 10 MHz to 200 MHz; Outputs: 12; Operating range: -40 to r='#FF0000'>85 C 单芯位CMOS微机r>r='#FF0000'>2-mbit (12r='#FF0000'>8r='#FF0000'>k r='#FF0000'>x 16) r='#FF0000'>static rAM; Density: 2 Mb; Organization: 12r='#FF0000'>8r='#FF0000'>kb r='#FF0000'>x 16; Vcc (V): 2.20 to 3.60 V; 单芯位CMOS微机r>SINGLE-CHIP r='#FF0000'>8-BIT CMOS MICrOCOMPUTEr 单芯r='#FF0000'>8位CMOS微机r>r='#FF0000'>2-mbit (r='#FF0000'>256r='#FF0000'>k r='#FF0000'>x r='#FF0000'>8) r='#FF0000'>static rAM; Density: 2 Mb; Organization: r='#FF0000'>256r='#FF0000'>kb r='#FF0000'>x r='#FF0000'>8; Vcc (V): 2.20 to 3.60 V; 单芯r='#FF0000'>8位CMOS微机r>Very Low Jitter Field and Factory Programmable Clocr='#FF0000'>k Generator; Voltage (V): 3.3 V; Input range: 10 MHz to 133 MHz; Output range: 20 MHz to 200 MHz; Outputs: 2 单芯位CMOS微机r>3.3V Zero Delay Clocr='#FF0000'>k Buffer; Voltage (V): 3.3 V; Frequency range: 10 MHz to 133 MHz; Outputs: 5; Operating range: 0 to 70 C 单芯位CMOS微机r>3.3V Zero Delay Clocr='#FF0000'>k Buffer; Voltage (V): 3.3 V; Frequency range: 10 MHz to 133 MHz; Outputs: 5; Operating range: -40 to r='#FF0000'>85 C 单芯位CMOS微机r>Three-PLL General Purpose FLASH Programmable Clocr='#FF0000'>k Generator; Voltage (V): 3.3 V; Input range: 1 MHz to 166 MHz; Output range: 0 MHz to 200 MHz; Outputs: 3 单芯位CMOS微机r>1:r='#FF0000'>8 Clocr='#FF0000'>k Fanout Buffer; Voltage (V): 3.3 V; Frequency range: 0 MHz to 350 MHz; Outputs: r='#FF0000'>8; Operating range: -40 to r='#FF0000'>85 C 单芯位CMOS微机r>Quad PLL Clocr='#FF0000'>k Generator with 2-Wire Serial Interface; Voltage (V): 2.5/3.3 V; Input range: 27 MHz to 27 MHz; Output range: 4.2 MHz to 166 MHz; Outputs: 5 单芯位CMOS微机r>2.5V or 3.3V, 200-MHz, 1:12 Clocr='#FF0000'>k Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency range: 0 MHz to 200 MHz; Outputs: 12; Operating range: 0 to 70 C 单芯位CMOS微机r>3.3V Zero Delay Clocr='#FF0000'>k Buffer; Voltage (V): 3.3 V; Frequency range: 10 MHz to 133 MHz; Outputs: 9; Operating range: 0 to 70 C 单芯位CMOS微机r>High Speed Multi-phase PLL Clocr='#FF0000'>k Buffer; Voltage (V): 3.3 V; Operating Frequency: 24 MHz to 200 MHz; Outputs: 11; Operating range: 0 to 70 C 单芯位CMOS微机r>2.5V or 3.3V, 200-MHz, 1:1r='#FF0000'>8 Clocr='#FF0000'>k Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency range: 0 MHz to 200 MHz; Outputs: 1r='#FF0000'>8; Operating range: -40 to r='#FF0000'>85 C 单芯位CMOS微机r>-bit AVr Microcontroller with r='#FF0000'>8r='#FF0000'>k Bytes In- System Programmable Flash 位AVr微控制器具有r='#FF0000'>8r='#FF0000'>k字节的系统内可编程闪r>2.5V or 3.3V, 200-MHz, 1:12 Clocr='#FF0000'>k Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency range: 0 MHz to 200 MHz; Outputs: 12; Operating range: 0 to 70 Cr>1:r='#FF0000'>8 Clocr='#FF0000'>k Fanout Buffer; Voltage (V): 3.3 V; Frequency range: 0 MHz to 350 MHz; Outputs: r='#FF0000'>8; Operating range: 0 to 70 Cr>Spread Spectrum Clocr='#FF0000'>k Generator; Voltage(V): 3.3 V; Input Frequency range: 4 MHz to 32 MHz; Output Frequency range: 4 MHz to 32 MHz; Operating range: 0 to 70 C; Pacr='#FF0000'>kage: SOICr>High Speed Low Voltage Programmable Sr='#FF0000'>kew Clocr='#FF0000'>k Buffer; Voltage (V): 3.3 V; Operating Frequency: 3.75 MHz to 110 MHz; Outputs: r='#FF0000'>8; Operating range: 0 to 70 Cr>5V, 3.3V, ISr(TM) High-Performance CPLDs; # Macrocells: 64; Vcc (V): 3.3; fMar='#FF0000'>x (MHz): 100; tPD (ns): 9r>
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