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For nnd - 4 mbit 512kb x8 or 256kb Found Datasheets File :: 150+       Page :: | 1 | 2 | 3 | <4> | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 |   

    MOTorOLA[Motorola Inc]
MOTorOLA[Motorola, Inc]
Part No. MCM72CB32SG66 MCM72CB32SG100 MCM72CB6or='#FF0000'>4SG80 MCM72CB32 MCM72CB32SG80 MCM72CB6or='#FF0000'>4SG100 MCM72CB6or='#FF0000'>4SG66
Description 256kb and or='#FF0000'>512kb BurstRAM Secondary Cache Module for Pentium
File Size 261.06K  /  14 Page

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    MOTorOLA[Motorola, Inc]
Part No. MCM72CF6or='#FF0000'>4SG66 MCM72CF32 MCM72CF32SG66
Description 256kb and or='#FF0000'>512kb BurstRAM Secondary Cache Module for Pentium
File Size 259.36K  /  14 Page

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    MOTorOLA[Motorola, Inc]
Part No. MCM36F7DG10 MCM36F6 MCM36F6DG10 MCM36F7
Description 256kb and or='#FF0000'>512kb Synchronous Fast Static RAM Module
File Size 118.61K  /  10 Page

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    MOTorOLA[Motorola, Inc]
Part No. MCM72BA6or='#FF0000'>4SG66 MCM72BA32 MCM72BA32SG50 MCM72BA32SG60 MCM72BA32SG66 MCM72BA6or='#FF0000'>4SG50 MCM72BA6or='#FF0000'>4SG60
Description 256kb and or='#FF0000'>512kb BurstRAM Secondary Cache Module for Pentium
File Size 237.49K  /  14 Page

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    MOTorOLA[Motorola, Inc]
Part No. MCM72BF6or='#FF0000'>4SG66 MCM72BF32 MCM72BF32SG60 MCM72BF32SG66 MCM72BF6or='#FF0000'>4SG60
Description 256kb and or='#FF0000'>512kb BurstRAM Secondary Cache Module for Pentium
File Size 254.14K  /  14 Page

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    http://
MOTorOLA[Motorola, Inc]
Part No. MCM72JG6or='#FF0000'>4SG66 MCM72JG32 MCM72JG32SG66
Description 256kb and or='#FF0000'>512kb Pipelined BurstRAM Secondary Cache Module for Pentium
File Size 296.26K  /  16 Page

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    Renesas Electronics Corporation.
Renesas Electronics, Corp.
Part No. M38030F2Lor='#FF0000'>-XXXHP M38030F2Lor='#FF0000'>-XXXKP M38030F2Lor='#FF0000'>-XXXSP M38030F2Lor='#FF0000'>-XXXWG M38030MALor='#FF0000'>-XXXWG M38030MALor='#FF0000'>-XXXKP M38030FALor='#FF0000'>-XXXSP M38031FALor='#FF0000'>-XXXHP M38030FALor='#FF0000'>-XXXWG M38030MALor='#FF0000'>-XXXHP M38030FALor='#FF0000'>-XXXKP M38031FALor='#FF0000'>-XXXKP M38030FALor='#FF0000'>-XXXHP M38031FALor='#FF0000'>-XXXSP M38031FALor='#FF0000'>-XXXWG M38030MALor='#FF0000'>-XXXSP M38030F3Lor='#FF0000'>-XXXHP M38030F3Lor='#FF0000'>-XXXWG M38030M3Lor='#FF0000'>-XXXKP M38030F3Lor='#FF0000'>-XXXSP M38030F3Lor='#FF0000'>-XXXKP M38030M3Lor='#FF0000'>-XXXHP M38030FBLor='#FF0000'>-XXXWG M38030MBLor='#FF0000'>-XXXHP M38030FBLor='#FF0000'>-XXXHP M38030FBLor='#FF0000'>-XXXSP M38030MBLor='#FF0000'>-XXXKP M38030M2Lor='#FF0000'>-XXXHP M38030M2Lor='#FF0000'>-XXXKP M38030M2Lor='#FF0000'>-XXXSP M38030M2Lor='#FF0000'>-XXXWG M38031F2Lor='#FF0000'>-XXXHP M38031F2Lor='#FF0000'>-XXXKP M38031F2Lor='#FF0000'>-XXXSP M38031F2Lor='#FF0000'>-XXXWG M38030FBor='#FF0000'>-XXXHP M38031FBLor='#FF0000'>-XXXSP M38035MBLor='#FF0000'>-XXXSP M38038FBLor='#FF0000'>-XXXSP M38039FBLor='#FF0000'>-XXXSP M38030MBLor='#FF0000'>-XXXSP M38036MBLor='#FF0000'>-XXXSP M38037FBLor='#FF0000'>-XXXSP M38037MBLor='#FF0000'>-XXXSP M38036FBLor='#FF0000'>-XXXSP M38038MBLor='#FF0000'>-XXXSP M38031FCor='#FF0000'>-XXXHP M38031FCor='#FF0000'>-XXXKP M38031FCor='#FF0000'>-XXXWG M38031FCLor='#FF0000'>-XXXHP M38031FCLor='#FF0000'>-XXXKP M38031FCLor='#FF0000'>-XXXSP M38031FCLor='#FF0000'>-XXXWG M38031F5or='#FF0000'>-XXXKP M38031F5or='#FF0000'>-XXXSP M38031F5or='#FF0000'>-XXXWG M38031F5Lor='#FF0000'>-XXXHP M38031F5Lor='#FF0000'>-XXXKP M38031F5Lor='#FF0000'>-XXXSP M38031F5Lor='#FF0000'>-XXXWG M38030F1or='#FF0000'>-XXXHP M38030F1or='#FF0000'>-XXXKP M38030F1or='#FF0000'>-XXXSP M38030F1or='#FF0000'>-XXXWG M38030F1Lor='#FF0000'>-XXXHP M38030F1Lor='#FF0000'>-XXXKP M38030F1Lor='#FF0000'>-XXXSP M38030F1Lor='#FF0000'>-XXXWG M38031F1or='#FF0000'>-XXXKP M38031F1or='#FF0000'>-XXXWG M38031F1Lor='#FF0000'>-XXXHP M38031F1Lor='#FF0000'>-XXXKP M38031F6or='#FF0000'>-XXXHP M38031F6or='#FF0000'>-XXXKP M38031F6or='#FF0000'>-XXXSP M38031F6or='#FF0000'>-XXXWG M
Description 256 Kbit (32K x 8) nvSRAM; organization: 32Kb x 8; Vcc (V): 2.7 to 3.6 V; Density: 256 Kb; Package: SOIC
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 5; Operating Range: 0 to 70 C
256K (32K x 8) Static RAM; Density: 256 Kb; organization: 32Kb x 8; Vcc (V): or='#FF0000'>4.50 to 5.50 V;
Threeor='#FF0000'>-PLL General Purpose FLASH Programmable Clock Generator; Voltage (V): 3.3 V; Input Range: 1 MHz to 166 MHz; Output Range: 1 MHz to 200 MHz; Outputs: 6
5V, 3.3V, ISR(TM) Highor='#FF0000'>-Performance CPLDs; # Macrocells: 256; Vcc (V): 3.3; fMax (MHz): 66; tPD (ns): 12
8or='#FF0000'>-or='#FF0000'>mbit (512K x 16) Static RAM; Density: 8 Mb; organization: or='#FF0000'>512kb x 16; Vcc (V): 2.20 to 3.60 V;
9or='#FF0000'>-or='#FF0000'>mbit (256K x 36/512K x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 9 Mb; organization: or='#FF0000'>512kb x 18; Vcc (V): 3.1 to 3.6 V
9or='#FF0000'>-or='#FF0000'>mbit (256K x 36/512K x 18) Flowor='#FF0000'>-Through SRAM; Architecture: Standard Sync, Flowor='#FF0000'>-through; Density: 9 Mb; organization: or='#FF0000'>512kb x 18; Vcc (V): 3.1 to 3.6 V
18or='#FF0000'>-or='#FF0000'>mbit QDR(TM)or='#FF0000'>-II SRAM or='#FF0000'>4or='#FF0000'>-Word Burst Architecture; Architecture: QDRor='#FF0000'>-II, or='#FF0000'>4 Word Burst; Density: 18 Mb; organization: or='#FF0000'>512kb x 36; Vcc (V): 1.7 to 1.9 V
Four Output PCIor='#FF0000'>-X and General Purpose Buffer; Voltage (V): 3.3 V; Frequency Range: 0 MHz to 1or='#FF0000'>40 MHz; Outputs: or='#FF0000'>4; Operating Range: 0 to 70 C
18or='#FF0000'>-or='#FF0000'>mbit QDR(TM)or='#FF0000'>-II SRAM 2or='#FF0000'>-Word Burst Architecture; Architecture: QDRor='#FF0000'>-II, 2 Word Burst; Density: 18 Mb; organization: or='#FF0000'>512kb x 36; Vcc (V): 1.7 to 1.9 V
9or='#FF0000'>-or='#FF0000'>mbit (256K x 36/512K x 18) Flowor='#FF0000'>-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flowor='#FF0000'>-through; Density: 9 Mb; organization: or='#FF0000'>512kb x 18; Vcc (V): 3.1 to 3.6 V
9or='#FF0000'>-or='#FF0000'>mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 9 Mb; organization: or='#FF0000'>512kb x 18; Vcc (V): 2.or='#FF0000'>4 to 2.6 V
or='#FF0000'>4or='#FF0000'>-or='#FF0000'>mbit (512K x 8) Static RAM; Density: or='#FF0000'>4 Mb; organization: or='#FF0000'>512kb x 8; Vcc (V): or='#FF0000'>4.50 to 5.50 V;
or='#FF0000'>4or='#FF0000'>-or='#FF0000'>mbit (256K x 16) Static RAM; Density: or='#FF0000'>4 Mb; organization: 256kb x 16; Vcc (V): 2.20 to 3.60 V;
6or='#FF0000'>4K x 16 Static RAM; Density: 1 Mb; organization: 6or='#FF0000'>4Kb x 16; Vcc (V): 3.0 to 3.6 V;
1or='#FF0000'>-or='#FF0000'>mbit (6or='#FF0000'>4K x 16) Static RAM; Density: 1 Mb; organization: 6or='#FF0000'>4Kb x 16; Vcc (V): or='#FF0000'>4.5 to 5.5 V;
9or='#FF0000'>-or='#FF0000'>mbit (256K x 36/512K x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 9 Mb; organization: 256kb x 36; Vcc (V): 3.1 to 3.6 V
1or='#FF0000'>-or='#FF0000'>mbit (6or='#FF0000'>4K x 16) Static RAM; Density: 1 Mb; organization: 6or='#FF0000'>4Kb x 16; Vcc (V): 3.0 to 3.6 V;
or='#FF0000'>4 or='#FF0000'>mbit (512K x 8/256K x 16) nvSRAM; organization: or='#FF0000'>512kb x 8; Vcc (V): 2.7 to 3.6 V; Density: or='#FF0000'>4 Mb; Package: TSOP
or='#FF0000'>4 or='#FF0000'>mbit (512K x 8/256K x 16) nvSRAM; organization: 256kb x 16; Vcc (V): 2.7 to 3.6 V; Density: or='#FF0000'>4 Mb; Package: TSOP
16or='#FF0000'>-or='#FF0000'>mbit (1M x 16 / 2M x 8) Static RAM; Density: 16 Mb; organization: 1Mb x 16; Vcc (V): or='#FF0000'>4.50 to 5.50 V;
or='#FF0000'>4K x 16/18 and 8K x 16/18 Dualor='#FF0000'>-Port Static RAM with SEM, INT, BUSY; Density: 128 Kb; organization: 8Kb x 16; Vcc (V): or='#FF0000'>4.5 to 5.5 V; Speed: 35 ns
9or='#FF0000'>-or='#FF0000'>mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 9 Mb; organization: 256kb x 36; Vcc (V): 3.1 to 3.6 V
9or='#FF0000'>-or='#FF0000'>mbit (256K x 36/512K x 18) Flowor='#FF0000'>-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flowor='#FF0000'>-through; Density: 9 Mb; organization: 256kb x 36; Vcc (V): 3.1 to 3.6 V
9or='#FF0000'>-or='#FF0000'>mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 9 Mb; organization: 256kb x 36; Vcc (V): 2.or='#FF0000'>4 to 2.6 V
9or='#FF0000'>-or='#FF0000'>mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 9 Mb; organization: or='#FF0000'>512kb x 18; Vcc (V): 3.1 to 3.6 V
8or='#FF0000'>-or='#FF0000'>mbit (512K x 16) Static RAM; Density: 8 Mb; organization: or='#FF0000'>512kb x 16; Vcc (V): or='#FF0000'>4.50 to 5.50 V;
9or='#FF0000'>-or='#FF0000'>mbit (256K x 36/512K x 18) Flowor='#FF0000'>-Through SRAM; Architecture: Standard Sync, Flowor='#FF0000'>-through; Density: 9 Mb; organization: 256kb x 36; Vcc (V): 3.1 to 3.6 V
256K x 16 Static RAM; Density: or='#FF0000'>4 Mb; organization: 256kb x 16; Vcc (V): or='#FF0000'>4.5 to 5.5 V;
9or='#FF0000'>-or='#FF0000'>mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM; Architecture: Standard Sync, Pipeline DCD; Density: 9 Mb; organization: 256kb x 36; Vcc (V): 3.1 to 3.6 V
or='#FF0000'>4or='#FF0000'>-or='#FF0000'>mbit (256K x 16) Static RAM; Density: or='#FF0000'>4 Mb; organization: 256kb x 16; Vcc (V): 3.0 to 3.6 V;
8or='#FF0000'>-or='#FF0000'>mbit (102or='#FF0000'>4K x 8) Static RAM; Density: 8 Mb; organization: 1Mb x 8; Vcc (V): 2.20 to 3.60 V;
18or='#FF0000'>-or='#FF0000'>mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 18 Mb; organization: or='#FF0000'>512kb x 36; Vcc (V): 3.1 to 3.6 V
256K x 16 Static RAM; Density: or='#FF0000'>4 Mb; organization: 256kb x 16; Vcc (V): 3.0 to 3.6 V;
8or='#FF0000'>-or='#FF0000'>mbit (1M x 8) Static RAM; Density: 8 Mb; organization: 1Mb x 8; Vcc (V): 2.20 to 3.60 V;
3.3V Zero Delay Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 8; Operating Range: or='#FF0000'>-or='#FF0000'>40 to 85 C
Programmable Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating Range: or='#FF0000'>-or='#FF0000'>40 to 85 C
18or='#FF0000'>-or='#FF0000'>mbit (512K x 36/1M x 18) Flowor='#FF0000'>-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flowor='#FF0000'>-through; Density: 18 Mb; organization: or='#FF0000'>512kb x 36; Vcc (V): 3.1 to 3.6 V
18or='#FF0000'>-or='#FF0000'>mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 18 Mb; organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
512K x 8 Static RAM; Density: or='#FF0000'>4 Mb; organization: or='#FF0000'>512kb x 8; Vcc (V): or='#FF0000'>4.5 to 5.5 V;
18or='#FF0000'>-or='#FF0000'>mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 18 Mb; organization: or='#FF0000'>512kb x 36; Vcc (V): 2.or='#FF0000'>4 to 2.6 V
2.5V or 3.3V, 200or='#FF0000'>-MHz, 1:12 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 MHz to 200 MHz; Outputs: 12; Operating Range: or='#FF0000'>-or='#FF0000'>40 to 85 C
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 5; Operating Range: or='#FF0000'>-or='#FF0000'>40 to 85 C
2M x 8 Static RAM; Density: 16 Mb; organization: 2Mb x 8; Vcc (V): 3.0 to 3.6 V;
16 or='#FF0000'>mbit (512K X 32) Static RAM; Density: 16 Mb; organization: or='#FF0000'>512kb x 32; Vcc (V): 3.0 to 3.6 V;
3.3V Zero Delay Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 8; Operating Range: 0 to 70 C
8or='#FF0000'>-or='#FF0000'>mbit (1M x 8) Static RAM; Density: 8 Mb; organization: 1Mb x 8; Vcc (V): 3.0 to 3.6 V;
5V, 3.3V, ISR(TM) Highor='#FF0000'>-Performance CPLDs; # Macrocells: 6or='#FF0000'>4; Vcc (V): 5; fMax (MHz): 125; tPD (ns): 6
2or='#FF0000'>-or='#FF0000'>mbit (128K x 16) Static RAM; Density: 2 Mb; organization: 128Kb x 16; Vcc (V): 3.0 to 3.6 V;
16or='#FF0000'>-or='#FF0000'>mbit (1M x 16) Static RAM; Density: 16 Mb; organization: 1Mb x 16; Vcc (V): 3.0 to 3.6 V;
or='#FF0000'>4or='#FF0000'>-or='#FF0000'>mbit (256K x 18) Pipelined DCD Sync SRAM; Architecture: Standard Sync, Pipeline DCD; Density: or='#FF0000'>4 Mb; organization: 256kb x 18; Vcc (V): 3.1 to 3.6 V
512K (32K x 16) Static RAM; Density: 512 Kb; organization: 32Kb x 16; Vcc (V): 3.0 to 3.6 V;
or='#FF0000'>4or='#FF0000'>-or='#FF0000'>mbit (128K x 36) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: or='#FF0000'>4 Mb; organization: 128Kb x 36; Vcc (V): 3.1 to 3.6 V
1M x 16 Static RAM; Density: 16 Mb; organization: 1Mb x 16; Vcc (V): 3.0 to 3.6 V;
Programmable Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating Range: 0 to 70 C
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 9; Operating Range: 0 to 70 C
MoBL(R) 2 or='#FF0000'>mbit (128K x 16) Static RAM; Density: 2 Mb; organization: 128Kb x 16; Vcc (V): 2.20 to 3.60 V;
Rambus(R) XDR(TM) Clock Generator; VDD: 2.5 V; Input Frequency: 100 MHz to 133 MHz; Output Frequency: 300 MHz to 800 MHz; # Out: or='#FF0000'>4
2or='#FF0000'>-or='#FF0000'>mbit (128K x 16) Static RAM; Density: 2 Mb; organization: 128Kb x 16; Vcc (V): 2.20 to 3.60 V;
or='#FF0000'>4or='#FF0000'>-or='#FF0000'>mbit (128K x 36) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: or='#FF0000'>4 Mb; organization: 128Kb x 36; Vcc (V): 3.1 to 3.6 V
5V, 3.3V, ISR(TM) Highor='#FF0000'>-Performance CPLDs; # Macrocells: 128; Vcc (V): 5; fMax (MHz): 167; tPD (ns): 7
2.5V or 3.3V, 200or='#FF0000'>-MHz, 1:10 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 MHz to 200 MHz; Outputs: 10; Operating Range: 0 to 70 C
5V, 3.3V, ISR(TM) Highor='#FF0000'>-Performance CPLDs; # Macrocells: 128; Vcc (V): 5; fMax (MHz): 100; tPD (ns): 7
5V, 3.3V, ISR(TM) Highor='#FF0000'>-Performance CPLDs; # Macrocells: 128; Vcc (V): 5; fMax (MHz): 125; tPD (ns): 7
18or='#FF0000'>-or='#FF0000'>mbit DDRor='#FF0000'>-II SRAM 2or='#FF0000'>-Word Burst Architecture; Architecture: DDRor='#FF0000'>-II CIO, 2 Word Burst; Density: 18 Mb; organization: or='#FF0000'>512kb x 36; Vcc (V): 1.7 to 1.9 V
Low Voltage Programmable Skew Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating Range: 0 to 70 C
Spread Spectrum Clock Generator; Voltage(V): 3.3 V; Input Frequency Range: 25 MHz to 100 MHz; Output Frequency Range: 25 MHz to 100 MHz; Operating Range: 0 to 70 C; Package: SOIC
Low Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating Range: 0 to 70 C
5V, 3.3V, ISR(TM) Highor='#FF0000'>-Performance CPLDs; # Macrocells: 6or='#FF0000'>4; Vcc (V): 3.3; fMax (MHz): 1or='#FF0000'>43; tPD (ns): 9 单芯位CMOS微机
5V, 3.3V, ISR(TM) Highor='#FF0000'>-Performance CPLDs; # Macrocells: 6or='#FF0000'>4; Vcc (V): 5; fMax (MHz): 15or='#FF0000'>4; tPD (ns): 6 单芯位CMOS微机
SINGLEor='#FF0000'>-CHIP 8or='#FF0000'>-BIT CMOS MICROCOMPUTER 单芯位CMOS微机
5V, 3.3V, ISR(TM) Highor='#FF0000'>-Performance CPLDs; # Macrocells: 6or='#FF0000'>4; Vcc (V): 3.3; fMax (MHz): 100; tPD (ns): 9 单芯位CMOS微机
5V, 3.3V, ISR(TM) Highor='#FF0000'>-Performance CPLDs; # Macrocells: 128; Vcc (V): 3.3; fMax (MHz): 83; tPD (ns): 10 单芯位CMOS微机
5V, 3.3V, ISR(TM) Highor='#FF0000'>-Performance CPLDs; # Macrocells: 6or='#FF0000'>4; Vcc (V): 5; fMax (MHz): 125; tPD (ns): 6 单芯位CMOS微机
Threeor='#FF0000'>-PLL Generalor='#FF0000'>-Purpose EPROM Programmable Clock Generator; Voltage (V): 3.3/5.0 V; Input Range: 1 MHz to 30 MHz; Output Range: .077 MHz to 100 MHz; Outputs: 6 单芯位CMOS微机
8or='#FF0000'>-or='#FF0000'>mbit (512K x 16) MoBL(R) Static RAM; Density: 8 Mb; organization: or='#FF0000'>512kb x 16; Vcc (V): 2.20 to 3.60 V; 单芯位CMOS微机
High Speed Low Voltage Programmable Skew Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 3.75 MHz to 110 MHz; Outputs: 8; Operating Range: 0 to 70 C 单芯位CMOS微机
3.3V SDRAM Buffer for Mobile PCs with or='#FF0000'>4 SOor='#FF0000'>-DIMMs; Voltage (V): 3.3 V; Frequency Range: 0 MHz to 100 MHz; Outputs: 10; Operating Range: 0 to 70 C 单芯位CMOS微机
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 9; Operating Range: or='#FF0000'>-or='#FF0000'>40 to 85 C 单芯位CMOS微机
Programmable Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating Range: or='#FF0000'>-or='#FF0000'>40 to 85 C 单芯位CMOS微机
2or='#FF0000'>-or='#FF0000'>mbit (128K x 16) Static RAM; Density: 2 Mb; organization: 128Kb x 16; Vcc (V): 3.0 to 3.6 V; 单芯位CMOS微机
MoBL(R) 1 or='#FF0000'>mbit (128K x 8) Static RAM; Density: 1 Mb; organization: 128Kb x 8; Vcc (V): 2.20 to 3.60 V; 单芯位CMOS微机
18or='#FF0000'>-or='#FF0000'>mbit QDR(TM)or='#FF0000'>-II SRAM 2or='#FF0000'>-Word Burst Architecture; Architecture: QDRor='#FF0000'>-II, 2 Word Burst; Density: 18 Mb; organization: 1Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
1or='#FF0000'>-or='#FF0000'>mbit (128K x 8) Static RAM; Density: 1 Mb; organization: 128Kb x 8; Vcc (V): or='#FF0000'>4.50 to 5.50 V; 单芯位CMOS微机
or='#FF0000'>4or='#FF0000'>-or='#FF0000'>mbit (256K x 18) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: or='#FF0000'>4 Mb; organization: 256kb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
2or='#FF0000'>-or='#FF0000'>mbit (6or='#FF0000'>4K x 32) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 2 Mb; organization: 6or='#FF0000'>4Kb x 32; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
200or='#FF0000'>-MHz Field Programmable Zero Delay Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 10 MHz to 200 MHz; Outputs: 12; Operating Range: or='#FF0000'>-or='#FF0000'>40 to 85 C 单芯位CMOS微机
2or='#FF0000'>-or='#FF0000'>mbit (128K x 16) Static RAM; Density: 2 Mb; organization: 128Kb x 16; Vcc (V): 2.20 to 3.60 V; 单芯位CMOS微机
SINGLEor='#FF0000'>-CHIP 8or='#FF0000'>-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机
2or='#FF0000'>-or='#FF0000'>mbit (256K x 8) Static RAM; Density: 2 Mb; organization: 256kb x 8; Vcc (V): 2.20 to 3.60 V; 单芯8位CMOS微机
Very Low Jitter Field and Factory Programmable Clock Generator; Voltage (V): 3.3 V; Input Range: 10 MHz to 133 MHz; Output Range: 20 MHz to 200 MHz; Outputs: 2 单芯位CMOS微机
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 5; Operating Range: 0 to 70 C 单芯位CMOS微机
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 5; Operating Range: or='#FF0000'>-or='#FF0000'>40 to 85 C 单芯位CMOS微机
Threeor='#FF0000'>-PLL General Purpose FLASH Programmable Clock Generator; Voltage (V): 3.3 V; Input Range: 1 MHz to 166 MHz; Output Range: 0 MHz to 200 MHz; Outputs: 3 单芯位CMOS微机
1:8 Clock Fanout Buffer; Voltage (V): 3.3 V; Frequency Range: 0 MHz to 350 MHz; Outputs: 8; Operating Range: or='#FF0000'>-or='#FF0000'>40 to 85 C 单芯位CMOS微机
Quad PLL Clock Generator with 2or='#FF0000'>-Wire Serial Interface; Voltage (V): 2.5/3.3 V; Input Range: 27 MHz to 27 MHz; Output Range: or='#FF0000'>4.2 MHz to 166 MHz; Outputs: 5 单芯位CMOS微机
2.5V or 3.3V, 200or='#FF0000'>-MHz, 1:12 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 MHz to 200 MHz; Outputs: 12; Operating Range: 0 to 70 C 单芯位CMOS微机
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 9; Operating Range: 0 to 70 C 单芯位CMOS微机
High Speed Multior='#FF0000'>-phase PLL Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 2or='#FF0000'>4 MHz to 200 MHz; Outputs: 11; Operating Range: 0 to 70 C 单芯位CMOS微机
2.5V or 3.3V, 200or='#FF0000'>-MHz, 1:18 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 MHz to 200 MHz; Outputs: 18; Operating Range: or='#FF0000'>-or='#FF0000'>40 to 85 C 单芯位CMOS微机
or='#FF0000'>-bit AVR Microcontroller with 8K Bytes Inor='#FF0000'>- System Programmable Flash 位AVR微控制器具有8K字节的系统内可编程闪
2.5V or 3.3V, 200or='#FF0000'>-MHz, 1:12 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 MHz to 200 MHz; Outputs: 12; Operating Range: 0 to 70 C
1:8 Clock Fanout Buffer; Voltage (V): 3.3 V; Frequency Range: 0 MHz to 350 MHz; Outputs: 8; Operating Range: 0 to 70 C
Spread Spectrum Clock Generator; Voltage(V): 3.3 V; Input Frequency Range: or='#FF0000'>4 MHz to 32 MHz; Output Frequency Range: or='#FF0000'>4 MHz to 32 MHz; Operating Range: 0 to 70 C; Package: SOIC
High Speed Low Voltage Programmable Skew Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 3.75 MHz to 110 MHz; Outputs: 8; Operating Range: 0 to 70 C
5V, 3.3V, ISR(TM) Highor='#FF0000'>-Performance CPLDs; # Macrocells: 6or='#FF0000'>4; Vcc (V): 3.3; fMax (MHz): 100; tPD (ns): 9
File Size 1,602.57K  /  119 Page

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    CXK79M72C164GB CXK79M36C164GB

Sony Corporation
Part No. CXK79M72C16or='#FF0000'>4GB CXK79M36C16or='#FF0000'>4GB
Description 18Mb 1x1Dp HSTL High Speed Synchronous SRAMs (256kb x 72 or or='#FF0000'>512kb x 36)
File Size 217.34K  /  28 Page

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    意法半导
Part No. M28For='#FF0000'>420
Description or='#FF0000'>4or='#FF0000'>mbit (or='#FF0000'>512kb or='#FF0000'>x8 or 256kb x16, Boot Block) Flash Memory(or='#FF0000'>4Mb闪速存储器)
File Size 18.20K  /  2 Page

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    CXK79M72C165GB CXK79M36C165GB

Sony Corporation
Part No. CXK79M72C165GB CXK79M36C165GB
Description 18Mb 1x1Dp LVCMOS High Speed Synchronous SRAMs (256kb x 72 or or='#FF0000'>512kb x 36)
File Size 199.18K  /  29 Page

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