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PMC[PMC-Sierra, Inc]
PMC-Serria
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| Part No. |
PM73122 PM73122-BI
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| OCR Text |
...FSET bit description. Clarified mvip-90 configuration in the Operations section Changed DC_INT from link to tributary. Flipped HIZDATA and HIZIO. In DC Characteristics, made operating current for I/O typical, added .5 ns margin to C1FP hold... |
| Description |
32 LINK CES/DBCES AAL1 SAR PROCESSOR
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| File Size |
4,214.11K /
489 Page |
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PMC-Sierra Inc
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| Part No. |
PM7381-PI
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| OCR Text |
...vendor integration protocol (h-mvip) ......................................................................................43 8.2 high-level data link control (hdlc) protocol.........43 8.3 receive channel assigner ........................ |
| Description |
32 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER WITH ANY-PHY PACKET INTERFACE
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| File Size |
1,941.86K /
224 Page |
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Zarlink
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| Part No. |
MT90810
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| OCR Text |
mvip Interface Circuit
Features
* * mvip and ST-BUS compliant
ISSUE 3
March 1997
Ordering Information MT90810AK 100 Pin PQFP 0 C to +70 C
* * *
* * * *
mvip Enhanced Switching with 384x384 channel capacity (256 mvip chan... |
| Description |
CMOS
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| File Size |
501.00K /
34 Page |
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PMC-Sierra Inc
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| Part No. |
PM4332 PM4332-PI
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| OCR Text |
... its customers ii 9.13 egress h-mvip system interface ................................... 70 9.14 ingress system h-mvip interface .................................. 72 9.15 extract scaleable bandwidth interconnect (exsbi) ..................... |
| Description |
HIGH DENSITY 32 CHANNEL T1/E1/J1 FRAMER
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| File Size |
3,651.80K /
446 Page |
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Lineage Power
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| Part No. |
T8105
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| OCR Text |
...ed loop (pll) for h.100/h.110, mvip *, or dialogic s ? sc-bus clock operation in master or slave clock modes n serial tdm bus rate and format conversion between most standard buses n optional 8-bit parallel input and/or 8-bit parallel ... |
| Description |
H.100/H.110 Interface and Time-Slot Interchanger(H.100/H.110接口和干线时隙交换机)
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| File Size |
216.41K /
4 Page |
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ZARLINK[Zarlink Semiconductor Inc]
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| Part No. |
ZL50117GAG2 ZL50116GAG ZL50116GAG2 ZL50117GAG ZL50120GAG2 ZL50115 ZL50115GAG ZL50115GAG2 ZL50116 ZL50117 ZL50117_06 ZL50118 ZL50118GAG ZL50118GAG2 ZL50119 ZL50119GAG ZL50119GAG2 ZL50120 ZL50120GAG
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| OCR Text |
...3/E3, or 1 STS-1 ports H.110, H-mvip, ST-BUS backplane
4 T1/E1, 1 J2/T3/E3 or 1 STS-1 ports H.110, H-mvip, ST-BUS backplanes
TDM Interface
(LIU, Framer, Backplane)
Multi-Protocol Packet Processing Engine
PW, RTP, UDP, IPv4, IPv6,... |
| Description |
32, 64 and 128 Channel CESoP Processors
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| File Size |
1,166.74K /
95 Page |
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Lineage Power
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| Part No. |
T8102
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| OCR Text |
...ed loop (pll) for h.100/h.110, mvip *, or dialogic s ? sc-bus clock operation in master or slave clock modes n serial tdm bus rate and format conversion between most standard buses n optional 8-bit parallel input and/or 8-bit parallel ... |
| Description |
H.100/H.110 Interface and Time-Slot Interchanger(H.100/H.110接口和干线时隙交换机)
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| File Size |
210.25K /
4 Page |
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Lineage Power
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| Part No. |
T8100
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| OCR Text |
...ed loop (pll) for h.100/h.110, mvip *, or dialogic s ? sc-bus clock operation in master or slave clock modes n serial tdm bus rate and format conversion between most standard buses n optional 8-bit parallel input and/or 8-bit parallel ... |
| Description |
H.100/H.110 Interface and Time-Slot Interchanger(H.100/H.110接口和干线时隙交换机)
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| File Size |
212.77K /
4 Page |
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it Online |
Download Datasheet |
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