| |
|
 |
TI store
|
| Part No. |
DSLVDS1001 DSLVDS1001DBVR DSLVDS1001DBVT
|
| OCR Text |
... the dslvds1001 accepts a 3.3-v lvcmos/lvttl input level and outputs low voltage ( 350 mv typical) differential signals that have low elect...to provide a high-speed lvds interface. device information (1) part number package body size (nom) d... |
| Description |
<font color=red>[Old version datasheet]</font> 3.3-V LVDS Single Channel High Speed Differential Driver
|
| File Size |
647.99K /
25 Page |
 View
it Online |
Download Datasheet
|
| |
|
|
TI store
|
| Part No. |
DSLVDS1001-18
|
| OCR Text |
... the dslvds1001 accepts a 3.3-v lvcmos/lvttl input level and outputs low voltage ( 350 mv typical) differential signals that have low elect...to provide a high-speed lvds interface. device information (1) part number package body size (nom) d... |
| Description |
<font color=red>[Old version datasheet]</font> 3.3-V LVDS Single Channel High Speed Differential Driver
|
| File Size |
649.66K /
25 Page |
View
it Online |
Download Datasheet |
| |
|
|
ON Semiconductor
|
| Part No. |
NB4N527S
|
| OCR Text |
...pecl, cml, hstl, lvds, or lvttl/lvcmos) to lvds. depending on the distance, noise immunity of the system design, and transmission line media, this device will receive, drive or translate data or clock signals up to 2.5 gb/s or 1.5 ghz, resp... |
| Description |
Translator, 3.3 V, 2.5 Gb/s Dual AnyLevel™ to LVDS Receiver/Driver/Buffer, with Internal Termination
|
| File Size |
167.06K /
10 Page |
View
it Online |
Download Datasheet |
| |
|
|
ON Semiconductor
|
| Part No. |
NB4N316M
|
| OCR Text |
...vel input signals: lvpecl, cml, lvcmos, lvttl, or lvds. these signals will be translated to cml, operating up to 2.0 ghz or 2.5 gb/s, respectively. as such, the nb4n316m is ideal for sonet, gige, fiber channel, backplane and other clock or ... |
| Description |
3.3 V AnyLevel Receiver to CML Driver/Translator with Input Hysteresis - 2.0 GHz Clock / 2.5 Gb/s Data
|
| File Size |
185.03K /
12 Page |
View
it Online |
Download Datasheet |
| |
|
|
Integrated Device Techn...
|
| Part No. |
IDT8T49N222I
|
| OCR Text |
...input pullup i 2 c clock input. lvcmos/lvttl interface levels. 19 reserved unused must be left unconnected. 20 s_a1 input pulldown i 2 c ad...to lvds or lvpecl interface levels. 29 oe1 input pullup active high output enable for q1, nq1. 0 = ... |
| Description |
Fourth generation FemtoClock
|
| File Size |
697.58K /
40 Page |
View
it Online |
Download Datasheet |
| |
|
|
Integrated Device Techn...
|
| Part No. |
IDT8T49N205I
|
| OCR Text |
...tive differential clock input. lvcmos/lvttl interface levels. 0 = clk0, nclk0 (default) 1 = clk1, nclk1 5 clk0 input pulldown non-inverting...to be left unconnected. 12 pll_bypas s input pulldown bypasses the vcxo pll. in bypass mode, output... |
| Description |
Fourth Generation FemtoClock
|
| File Size |
732.27K /
41 Page |
View
it Online |
Download Datasheet |
| |
|
|
Integrated Device Techn...
|
| Part No. |
IDT8T49N203I
|
| OCR Text |
...ive differential clock i nput. lvcmos/lvttl interface levels. 0 = clk0, nclk0 (default) 1 = clk1, nclk1 5 clk0 input pulldown non-invertin...to be left unconnected. 12 pll_bypass input pulldown bypasses the vcxo pll. in bypass mode, outputs... |
| Description |
Fourth generation FemtoClock
|
| File Size |
1,213.92K /
40 Page |
View
it Online |
Download Datasheet |
| |
|
|
Integrated Device Techn...
|
| Part No. |
DT8T49N243NLGI
|
| OCR Text |
...ct among lvpecl, lvds, hcsl or lvcmos output levels. this makes it ideal to be used in any frequency synthesis application, including 1g, 10g, 40g and 100g synchronous ethernet, otn, and sonet/sdh, including itu-t g.709 (2009) fec rates... |
| Description |
FemtoClock NG Universal Frequency Translator
|
| File Size |
1,198.47K /
59 Page |
View
it Online |
Download Datasheet |
|
Price and Availability
|
