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Integrated Device Technology, Inc.
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| Part No. |
IDT723656
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| OCR Text |
...through a port are gated to the low-to-high transition of a port clock by enable signals. the clocks for description the idt723656/723666/7...if interspersed parity is selected then during parallel programming of the flag offset values, the d... |
| Description |
2K x 36 x 2 Triple-Bus FIFO, 5.0V
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| File Size |
335.95K /
39 Page |
 View
it Online |
Download Datasheet
|
| |
|
|
Integrated Device Technology, Inc.
|
| Part No. |
IDT723663
|
| OCR Text |
...through a port are gated to the low-to-high transition of a port clock by enable signals. the clocks for each port are independent of one an...if interspersed parity is selected then during parallel programming of the flag offset values, the d... |
| Description |
4K x 36 SyncFIFO, 5.0V
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| File Size |
294.36K /
29 Page |
View
it Online |
Download Datasheet |
|
Price and Availability
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