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						|  |  |  | ICS 
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						| Part No. | ICS85408I 
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						| OCR Text | ...ls: LVPECL, LVDS, LVHSTL, SSTL, hcsl * Maximum output frequency: 700MHz * Translates any differential input signal (LVPECL, LVHSTL, SSTL, hcsl) to LVDS levels without external bias networks * Translates any single-ended input signal to LVDS... |  
						| Description | Low Skew, 1-to-8 Differential-to-LVDS Fanout Buffer. Industrial Temp. 
 
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						| File Size | 160.19K  / 
						12 Page | 
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 ICS
 Integrated Circuit Systems
 
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						| Part No. | ICS85408 ICS85408BG ICS85408BGLF ICS85408BGLFT ICS85408BGT 
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						| OCR Text | ...ls: LVPECL, LVDS, LVHSTL, SSTL, hcsl * Maximum output frequency: 700MHz * Translates any differential input signal (LVPECL, LVHSTL, SSTL, hcsl) to LVDS levels without external bias networks * Translates any single-ended input signal to LVDS... |  
						| Description | Low Skew, 1-to-8, Differential-to-LVDS Fanout Buffer LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
 
 
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						| File Size | 168.14K  / 
						12 Page | 
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						|  |  |  | Integrated Device Techn... 
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						| Part No. | ICS851010I 
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						| OCR Text | hcsl fanout buffer ics851010i general description the ics851010i is a 1-to-10 differential hcsl fanout buffer. the  ics851010i is designed to translate any differential signal levels to  differential hcsl output levels. an external referenc... |  
						| Description | 1-to-10, Differential hcsl Fanout Buffer 
 
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						| File Size | 675.39K  / 
						17 Page | 
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						|  |  |  | Integrated Device Techn... 
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						| Part No. | 9DML0441 
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						| OCR Text | ...ures ? four 1?200mhz low-power  hcsl (lp-hcsl) dif pairs ? 9dml0441 default z out  = 100 ? ? 9dml0451 default z out  = 85 ? ? 9dml04p1 factory programmable defaults ? see  an-891  for easy termination to other logic levels features ? direct... |  
						| Description | 2:4 3.3V PCIe Clock Mux 
 
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						| File Size | 227.48K  / 
						10 Page | 
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						|  |  |  | Discera 
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						| Part No. | DSC557-03 
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						| OCR Text | ...tion  of   lvpecl,  lvds,  and  hcsl.       block diagram     *   clk0+/ -   and clk1+/ -   are 100 mhz as per pcie  standards.  for other frequencies, please  contact the factory.     features   ?      ?   o hcsl, lvpecl, or lv ds   o hcsl... |  
						| Description | Crystal-less Two Output PCIe Gen1/2/3 Clock Generator 
 
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						| File Size | 564.10K  / 
						9 Page | 
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						|  |  |  | Integrated Device Techn... 
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						| Part No. | 5V49EE902NLGI 5V49EE902NLGI8 
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						| OCR Text | ...support lvttl, lvpecl, lvds  or hcsl logic levels. out0 (output 0) supports 3.3v  single-ended output only. the outputs are connected to the  plls via a switch matrix. the switch matrix allows the user  to route the pll outputs to any outpu... |  
						| Description | EEPROM PROGRAMMABLE CLOCK GENERATOR 
 
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						| File Size | 332.67K  / 
						33 Page | 
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