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differential-to-hstl Datasheet PDF File

For differential-to-hstl Found Datasheets File :: 880 Search Time::2ms
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				Maxim Integrated Products, Inc. MAXIM - Dallas Semiconductor
Part No.	MAX9312 MAX9314 MAX9312ECJ
OCR Text	Differential LVPECL/LVECL/HSTL Clock and Data Drivers General Description The MAX9312/MAX9314 are low skew, dual 1-to-5 differential drivers designed for clock and data distribution. These devices accept two inputs. Each input is reproduc...
Description	Dual 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Drivers LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 Dual 1:5 Differential LVPECL/ LVECL/HSTL Clock and Data Drivers
File Size	334.12K / 11 Page	View it Online	Download Datasheet

				Maxim Integrated Products
Part No.	MAX9321-BMAX9321A
OCR Text	Differential LVPECL/LVECL/HSTL Receiver/Drivers General Description The MAX9321/MAX9321A are low-skew differential receiver/drivers design...to accept a single-ended input by connecting the on-chip VBB supply to an input as a reference volta...
Description	Differential LVPECL/LVECL/HSTL Receiver/Drivers
File Size	142.56K / 9 Page	View it Online	Download Datasheet

				ALTERA
Part No.	EP20K100EQ EP20K100QC EP20K100EQC240-2
OCR Text	...tandards, including low-voltage differential signaling (LVDS), LVPECL, PCI-X, AGP, CTT, stubseries terminated logic (SSTL-3 and SSTL-2), Gun...to drive 29 other LEs through the fast local interconnect Advanced packaging options - Available in ...
Description	Apex 20KE Device Family (1.8V, LVDS Apex 20K Device Family (2.5V)
File Size	585.74K / 116 Page	View it Online	Download Datasheet

				LATTICE[Lattice Semiconductor]
Part No.	ISPPAC-CLK5510V ISPPAC-CLK5510V-01T48I ISPPAC-CLK5510V-01T48C ISPPAC-CLK5520V-01T100C ISPPAC-CLK5520V-01T100I ISPPAC-CLK5520V-01TN100C ISPPAC-CLK5520V-01TN100I ISPPAC-CLK55XX ISPPAC-CLK5510V-01TN48C ISPPAC-CLK5510V-01TN48I
OCR Text	...s up to 10 single-ended or five differential clock outputs, while the ispClock5520 provides up to 20 single-ended or 10 differential clock outputs. Each pair of outputs may be independently configured to support separate I/O standards (LVDS...
Description	In-System Programmable Clock Generator with Universal Fan-Out Buffer
File Size	794.03K / 43 Page	View it Online	Download Datasheet

				XILINX[Xilinx, Inc] Xilinx, Inc.
Part No.	XCV405E-8BG560C XCV405E-8BG560I XCV405E-8FG560C XCV405E-8FG560I XCV405E-6BG560C XCV405E-6BG560I XCV405E-6FG560C XCV405E-6FG560I XCV405E XCV812E XCV405E-7BG560C XCV405E-7BG560I XCV405E-7FG560C XCV405E-7FG560I BG560
OCR Text	...singled-ended I/Os or up to 201 differential I/O pairs for an aggregate bandwidth of >100 Gb/s Complete Industry-Standard Differential Signalling Support - LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL - Al I/O signals can be input, output, or ...
Description	Fast, Extended Block RAM, 1.8 V FPGA Family Extended Memory Field Programmable Gate Arrays
File Size	36.65K / 4 Page	View it Online	Download Datasheet

				ICST[Integrated Circuit Systems]
Part No.	ICS844071I ICS844071AGI ICS844071AGIT
OCR Text	Differential LVDS output * Crystal oscillator interface, 18pF parallel resonant crystal (20.833MHz - 28.3MHz) * Output frequency range: 62.5...to 85C ambient operating temperature * Replaces ICS844051-11 GENERAL DESCRIPTION The ICS844071I ...
Description	FEMTOCLOCKS?/a> CRYSTAL-TO- LVDS CLOCK GENERATOR FEMTOCLOCKS⑩ CRYSTAL-TO- LVDS CLOCK GENERATOR FEMTOCLOCKS CRYSTAL-TO- LVDS CLOCK GENERATOR
File Size	157.04K / 10 Page	View it Online	Download Datasheet

				ON Semi
Part No.	XC100EP111 ON3015
OCR Text	Differential ECL/PECL/HSTL Clock Driver The XC100EP111 is a low skew 1-to-10 differential driver, designed with clock distribution in mind. It accepts two clock sources into an input multiplexer. The ECL/PECL input signals can be either di...
Description	LOW-VOLTAGE 1:10 DIFFERENTIAL ECL/PECL/HSTLCLOCK DRIVER From old datasheet system
File Size	128.97K / 8 Page	View it Online	Download Datasheet

				ICS
Part No.	ICS8422002I-01
OCR Text	...No connect. Output supply pins. Differential output pair. LVHSTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs nQx Pulldown to go...
Description	FemtoClocks? LVHSTL Frequency Synthesizer
File Size	187.17K / 13 Page	View it Online	Download Datasheet

For differential-to-hstl Found Datasheets File :: 880 Search Time::2ms
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