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Renesas Electronics Clor='#FF0000'>orplor='#FF0000'>oration.
Renesas Electronics, Clor='#FF0000'>orp.
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| Part No. |
M38030F2l-XXXHP M38030F2l-XXXKP M38030F2l-XXXSP M38030F2l-XXXWG M38030MAl-XXXWG M38030MAl-XXXKP M38030FAl-XXXSP M38031FAl-XXXHP M38030FAl-XXXWG M38030MAl-XXXHP M38030FAl-XXXKP M38031FAl-XXXKP M38030FAl-XXXHP M38031FAl-XXXSP M38031FAl-XXXWG M38030MAl-XXXSP M38030F3l-XXXHP M38030F3l-XXXWG M38030M3l-XXXKP M38030F3l-XXXSP M38030F3l-XXXKP M38030M3l-XXXHP M38030FBl-XXXWG M38030MBl-XXXHP M38030FBl-XXXHP M38030FBl-XXXSP M38030MBl-XXXKP M38030M2l-XXXHP M38030M2l-XXXKP M38030M2l-XXXSP M38030M2l-XXXWG M38031F2l-XXXHP M38031F2l-XXXKP M38031F2l-XXXSP M38031F2l-XXXWG M38030FB-XXXHP M38031FBl-XXXSP M38035MBl-XXXSP M38038FBl-XXXSP M38039FBl-XXXSP M38030MBl-XXXSP M38036MBl-XXXSP M38037FBl-XXXSP M38037MBl-XXXSP M38036FBl-XXXSP M38038MBl-XXXSP M38031FC-XXXHP M38031FC-XXXKP M38031FC-XXXWG M38031FCl-XXXHP M38031FCl-XXXKP M38031FCl-XXXSP M38031FCl-XXXWG M38031F5-XXXKP M38031F5-XXXSP M38031F5-XXXWG M38031F5l-XXXHP M38031F5l-XXXKP M38031F5l-XXXSP M38031F5l-XXXWG M38030F1-XXXHP M38030F1-XXXKP M38030F1-XXXSP M38030F1-XXXWG M38030F1l-XXXHP M38030F1l-XXXKP M38030F1l-XXXSP M38030F1l-XXXWG M38031F1-XXXKP M38031F1-XXXWG M38031F1l-XXXHP M38031F1l-XXXKP M38031F6-XXXHP M38031F6-XXXKP M38031F6-XXXSP M38031F6-XXXWG M
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| Description |
256 Kbit (32K x 8) nvSRAM; lor='#FF0000'>organization: 32Kb x 8; Vcc (V): 2.7 to 3.6 V; Density: 256 Kb; Package: SOIC
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 5; Operating Range: 0 to 70 C
256K (32K x 8) Static RAM; Density: 256 Kb; lor='#FF0000'>organization: 32Kb x 8; Vcc (V): llor='#FF0000'>or='#FF0000'>4.50 to 5.50 V;
Three-Pll General Purpose FlASH Programmable Clock Generatlor='#FF0000'>or; Voltage (V): 3.3 V; Input Range: 1 MHz to 166 MHz; Output Range: 1 MHz to 200 MHz; Outputs: 6
5V, 3.3V, ISR(TM) High-Perflor='#FF0000'>ormance CPlDs; # Macrocells: 256; Vcc (V): 3.3; fMax (MHz): 66; tPD (ns): 12
8-llor='#FF0000'>or='#FF0000'>mbit (512K x 16) Static RAM; Density: 8 Mb; lor='#FF0000'>organization: llor='#FF0000'>or='#FF0000'>512kb x 16; Vcc (V): 2.20 to 3.60 V;
9-llor='#FF0000'>or='#FF0000'>mbit (256K x 36/512K x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 9 Mb; lor='#FF0000'>organization: llor='#FF0000'>or='#FF0000'>512kb x 18; Vcc (V): 3.1 to 3.6 V
9-llor='#FF0000'>or='#FF0000'>mbit (256K x 36/512K x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 9 Mb; lor='#FF0000'>organization: llor='#FF0000'>or='#FF0000'>512kb x 18; Vcc (V): 3.1 to 3.6 V
18-llor='#FF0000'>or='#FF0000'>mbit QDR(TM)-II SRAM llor='#FF0000'>or='#FF0000'>4-Wlor='#FF0000'>ord Burst Architecture; Architecture: QDR-II, llor='#FF0000'>or='#FF0000'>4 Wlor='#FF0000'>ord Burst; Density: 18 Mb; lor='#FF0000'>organization: llor='#FF0000'>or='#FF0000'>512kb x 36; Vcc (V): 1.7 to 1.9 V
Four Output PCI-X and General Purpose Buffer; Voltage (V): 3.3 V; Frequency Range: 0 MHz to 1llor='#FF0000'>or='#FF0000'>40 MHz; Outputs: llor='#FF0000'>or='#FF0000'>4; Operating Range: 0 to 70 C
18-llor='#FF0000'>or='#FF0000'>mbit QDR(TM)-II SRAM 2-Wlor='#FF0000'>ord Burst Architecture; Architecture: QDR-II, 2 Wlor='#FF0000'>ord Burst; Density: 18 Mb; lor='#FF0000'>organization: llor='#FF0000'>or='#FF0000'>512kb x 36; Vcc (V): 1.7 to 1.9 V
9-llor='#FF0000'>or='#FF0000'>mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBl(TM) Architecture; Architecture: NoBl, Flow-through; Density: 9 Mb; lor='#FF0000'>organization: llor='#FF0000'>or='#FF0000'>512kb x 18; Vcc (V): 3.1 to 3.6 V
9-llor='#FF0000'>or='#FF0000'>mbit (256K x 36/512K x 18) Pipelined SRAM with NoBl(TM) Architecture; Architecture: NoBl, Pipeline; Density: 9 Mb; lor='#FF0000'>organization: llor='#FF0000'>or='#FF0000'>512kb x 18; Vcc (V): 2.llor='#FF0000'>or='#FF0000'>4 to 2.6 V
llor='#FF0000'>or='#FF0000'>4-llor='#FF0000'>or='#FF0000'>mbit (512K x 8) Static RAM; Density: llor='#FF0000'>or='#FF0000'>4 Mb; lor='#FF0000'>organization: llor='#FF0000'>or='#FF0000'>512kb x 8; Vcc (V): llor='#FF0000'>or='#FF0000'>4.50 to 5.50 V;
llor='#FF0000'>or='#FF0000'>4-llor='#FF0000'>or='#FF0000'>mbit (256K x 16) Static RAM; Density: llor='#FF0000'>or='#FF0000'>4 Mb; lor='#FF0000'>organization: lor='#FF0000'>256kb x 16; Vcc (V): 2.20 to 3.60 V;
6llor='#FF0000'>or='#FF0000'>4K x 16 Static RAM; Density: 1 Mb; lor='#FF0000'>organization: 6llor='#FF0000'>or='#FF0000'>4Kb x 16; Vcc (V): 3.0 to 3.6 V;
1-llor='#FF0000'>or='#FF0000'>mbit (6llor='#FF0000'>or='#FF0000'>4K x 16) Static RAM; Density: 1 Mb; lor='#FF0000'>organization: 6llor='#FF0000'>or='#FF0000'>4Kb x 16; Vcc (V): llor='#FF0000'>or='#FF0000'>4.5 to 5.5 V;
9-llor='#FF0000'>or='#FF0000'>mbit (256K x 36/512K x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 9 Mb; lor='#FF0000'>organization: lor='#FF0000'>256kb x 36; Vcc (V): 3.1 to 3.6 V
1-llor='#FF0000'>or='#FF0000'>mbit (6llor='#FF0000'>or='#FF0000'>4K x 16) Static RAM; Density: 1 Mb; lor='#FF0000'>organization: 6llor='#FF0000'>or='#FF0000'>4Kb x 16; Vcc (V): 3.0 to 3.6 V;
llor='#FF0000'>or='#FF0000'>4 llor='#FF0000'>or='#FF0000'>mbit (512K x 8/256K x 16) nvSRAM; lor='#FF0000'>organization: llor='#FF0000'>or='#FF0000'>512kb x 8; Vcc (V): 2.7 to 3.6 V; Density: llor='#FF0000'>or='#FF0000'>4 Mb; Package: TSOP
llor='#FF0000'>or='#FF0000'>4 llor='#FF0000'>or='#FF0000'>mbit (512K x 8/256K x 16) nvSRAM; lor='#FF0000'>organization: lor='#FF0000'>256kb x 16; Vcc (V): 2.7 to 3.6 V; Density: llor='#FF0000'>or='#FF0000'>4 Mb; Package: TSOP
16-llor='#FF0000'>or='#FF0000'>mbit (1M x 16 / 2M x 8) Static RAM; Density: 16 Mb; lor='#FF0000'>organization: 1Mb x 16; Vcc (V): llor='#FF0000'>or='#FF0000'>4.50 to 5.50 V;
llor='#FF0000'>or='#FF0000'>4K x 16/18 and 8K x 16/18 Dual-Plor='#FF0000'>ort Static RAM with SEM, INT, BUSY; Density: 128 Kb; lor='#FF0000'>organization: 8Kb x 16; Vcc (V): llor='#FF0000'>or='#FF0000'>4.5 to 5.5 V; Speed: 35 ns
9-llor='#FF0000'>or='#FF0000'>mbit (256K x 36/512K x 18) Pipelined SRAM with NoBl(TM) Architecture; Architecture: NoBl, Pipeline; Density: 9 Mb; lor='#FF0000'>organization: lor='#FF0000'>256kb x 36; Vcc (V): 3.1 to 3.6 V
9-llor='#FF0000'>or='#FF0000'>mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBl(TM) Architecture; Architecture: NoBl, Flow-through; Density: 9 Mb; lor='#FF0000'>organization: lor='#FF0000'>256kb x 36; Vcc (V): 3.1 to 3.6 V
9-llor='#FF0000'>or='#FF0000'>mbit (256K x 36/512K x 18) Pipelined SRAM with NoBl(TM) Architecture; Architecture: NoBl, Pipeline; Density: 9 Mb; lor='#FF0000'>organization: lor='#FF0000'>256kb x 36; Vcc (V): 2.llor='#FF0000'>or='#FF0000'>4 to 2.6 V
9-llor='#FF0000'>or='#FF0000'>mbit (256K x 36/512K x 18) Pipelined SRAM with NoBl(TM) Architecture; Architecture: NoBl, Pipeline; Density: 9 Mb; lor='#FF0000'>organization: llor='#FF0000'>or='#FF0000'>512kb x 18; Vcc (V): 3.1 to 3.6 V
8-llor='#FF0000'>or='#FF0000'>mbit (512K x 16) Static RAM; Density: 8 Mb; lor='#FF0000'>organization: llor='#FF0000'>or='#FF0000'>512kb x 16; Vcc (V): llor='#FF0000'>or='#FF0000'>4.50 to 5.50 V;
9-llor='#FF0000'>or='#FF0000'>mbit (256K x 36/512K x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 9 Mb; lor='#FF0000'>organization: lor='#FF0000'>256kb x 36; Vcc (V): 3.1 to 3.6 V
256K x 16 Static RAM; Density: llor='#FF0000'>or='#FF0000'>4 Mb; lor='#FF0000'>organization: lor='#FF0000'>256kb x 16; Vcc (V): llor='#FF0000'>or='#FF0000'>4.5 to 5.5 V;
9-llor='#FF0000'>or='#FF0000'>mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM; Architecture: Standard Sync, Pipeline DCD; Density: 9 Mb; lor='#FF0000'>organization: lor='#FF0000'>256kb x 36; Vcc (V): 3.1 to 3.6 V
llor='#FF0000'>or='#FF0000'>4-llor='#FF0000'>or='#FF0000'>mbit (256K x 16) Static RAM; Density: llor='#FF0000'>or='#FF0000'>4 Mb; lor='#FF0000'>organization: lor='#FF0000'>256kb x 16; Vcc (V): 3.0 to 3.6 V;
8-llor='#FF0000'>or='#FF0000'>mbit (102llor='#FF0000'>or='#FF0000'>4K x 8) Static RAM; Density: 8 Mb; lor='#FF0000'>organization: 1Mb x 8; Vcc (V): 2.20 to 3.60 V;
18-llor='#FF0000'>or='#FF0000'>mbit (512K x 36/1M x 18) Pipelined SRAM with NoBl(TM) Architecture; Architecture: NoBl, Pipeline; Density: 18 Mb; lor='#FF0000'>organization: llor='#FF0000'>or='#FF0000'>512kb x 36; Vcc (V): 3.1 to 3.6 V
256K x 16 Static RAM; Density: llor='#FF0000'>or='#FF0000'>4 Mb; lor='#FF0000'>organization: lor='#FF0000'>256kb x 16; Vcc (V): 3.0 to 3.6 V;
8-llor='#FF0000'>or='#FF0000'>mbit (1M x 8) Static RAM; Density: 8 Mb; lor='#FF0000'>organization: 1Mb x 8; Vcc (V): 2.20 to 3.60 V;
3.3V Zero Delay Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 8; Operating Range: -llor='#FF0000'>or='#FF0000'>40 to 85 C
Programmable Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating Range: -llor='#FF0000'>or='#FF0000'>40 to 85 C
18-llor='#FF0000'>or='#FF0000'>mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBl(TM) Architecture; Architecture: NoBl, Flow-through; Density: 18 Mb; lor='#FF0000'>organization: llor='#FF0000'>or='#FF0000'>512kb x 36; Vcc (V): 3.1 to 3.6 V
18-llor='#FF0000'>or='#FF0000'>mbit (512K x 36/1M x 18) Pipelined SRAM with NoBl(TM) Architecture; Architecture: NoBl, Pipeline; Density: 18 Mb; lor='#FF0000'>organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
512K x 8 Static RAM; Density: llor='#FF0000'>or='#FF0000'>4 Mb; lor='#FF0000'>organization: llor='#FF0000'>or='#FF0000'>512kb x 8; Vcc (V): llor='#FF0000'>or='#FF0000'>4.5 to 5.5 V;
18-llor='#FF0000'>or='#FF0000'>mbit (512K x 36/1M x 18) Pipelined SRAM with NoBl(TM) Architecture; Architecture: NoBl, Pipeline; Density: 18 Mb; lor='#FF0000'>organization: llor='#FF0000'>or='#FF0000'>512kb x 36; Vcc (V): 2.llor='#FF0000'>or='#FF0000'>4 to 2.6 V
2.5V lor='#FF0000'>or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 MHz to 200 MHz; Outputs: 12; Operating Range: -llor='#FF0000'>or='#FF0000'>40 to 85 C
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 5; Operating Range: -llor='#FF0000'>or='#FF0000'>40 to 85 C
2M x 8 Static RAM; Density: 16 Mb; lor='#FF0000'>organization: 2Mb x 8; Vcc (V): 3.0 to 3.6 V;
16 llor='#FF0000'>or='#FF0000'>mbit (512K X 32) Static RAM; Density: 16 Mb; lor='#FF0000'>organization: llor='#FF0000'>or='#FF0000'>512kb x 32; Vcc (V): 3.0 to 3.6 V;
3.3V Zero Delay Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 8; Operating Range: 0 to 70 C
8-llor='#FF0000'>or='#FF0000'>mbit (1M x 8) Static RAM; Density: 8 Mb; lor='#FF0000'>organization: 1Mb x 8; Vcc (V): 3.0 to 3.6 V;
5V, 3.3V, ISR(TM) High-Perflor='#FF0000'>ormance CPlDs; # Macrocells: 6llor='#FF0000'>or='#FF0000'>4; Vcc (V): 5; fMax (MHz): 125; tPD (ns): 6
2-llor='#FF0000'>or='#FF0000'>mbit (128K x 16) Static RAM; Density: 2 Mb; lor='#FF0000'>organization: 128Kb x 16; Vcc (V): 3.0 to 3.6 V;
16-llor='#FF0000'>or='#FF0000'>mbit (1M x 16) Static RAM; Density: 16 Mb; lor='#FF0000'>organization: 1Mb x 16; Vcc (V): 3.0 to 3.6 V;
llor='#FF0000'>or='#FF0000'>4-llor='#FF0000'>or='#FF0000'>mbit (256K x 18) Pipelined DCD Sync SRAM; Architecture: Standard Sync, Pipeline DCD; Density: llor='#FF0000'>or='#FF0000'>4 Mb; lor='#FF0000'>organization: lor='#FF0000'>256kb x 18; Vcc (V): 3.1 to 3.6 V
512K (32K x 16) Static RAM; Density: 512 Kb; lor='#FF0000'>organization: 32Kb x 16; Vcc (V): 3.0 to 3.6 V;
llor='#FF0000'>or='#FF0000'>4-llor='#FF0000'>or='#FF0000'>mbit (128K x 36) Pipelined SRAM with NoBl(TM) Architecture; Architecture: NoBl, Pipeline; Density: llor='#FF0000'>or='#FF0000'>4 Mb; lor='#FF0000'>organization: 128Kb x 36; Vcc (V): 3.1 to 3.6 V
1M x 16 Static RAM; Density: 16 Mb; lor='#FF0000'>organization: 1Mb x 16; Vcc (V): 3.0 to 3.6 V;
Programmable Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating Range: 0 to 70 C
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 9; Operating Range: 0 to 70 C
MoBl(R) 2 llor='#FF0000'>or='#FF0000'>mbit (128K x 16) Static RAM; Density: 2 Mb; lor='#FF0000'>organization: 128Kb x 16; Vcc (V): 2.20 to 3.60 V;
Rambus(R) XDR(TM) Clock Generatlor='#FF0000'>or; VDD: 2.5 V; Input Frequency: 100 MHz to 133 MHz; Output Frequency: 300 MHz to 800 MHz; # Out: llor='#FF0000'>or='#FF0000'>4
2-llor='#FF0000'>or='#FF0000'>mbit (128K x 16) Static RAM; Density: 2 Mb; lor='#FF0000'>organization: 128Kb x 16; Vcc (V): 2.20 to 3.60 V;
llor='#FF0000'>or='#FF0000'>4-llor='#FF0000'>or='#FF0000'>mbit (128K x 36) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: llor='#FF0000'>or='#FF0000'>4 Mb; lor='#FF0000'>organization: 128Kb x 36; Vcc (V): 3.1 to 3.6 V
5V, 3.3V, ISR(TM) High-Perflor='#FF0000'>ormance CPlDs; # Macrocells: 128; Vcc (V): 5; fMax (MHz): 167; tPD (ns): 7
2.5V lor='#FF0000'>or 3.3V, 200-MHz, 1:10 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 MHz to 200 MHz; Outputs: 10; Operating Range: 0 to 70 C
5V, 3.3V, ISR(TM) High-Perflor='#FF0000'>ormance CPlDs; # Macrocells: 128; Vcc (V): 5; fMax (MHz): 100; tPD (ns): 7
5V, 3.3V, ISR(TM) High-Perflor='#FF0000'>ormance CPlDs; # Macrocells: 128; Vcc (V): 5; fMax (MHz): 125; tPD (ns): 7
18-llor='#FF0000'>or='#FF0000'>mbit DDR-II SRAM 2-Wlor='#FF0000'>ord Burst Architecture; Architecture: DDR-II CIO, 2 Wlor='#FF0000'>ord Burst; Density: 18 Mb; lor='#FF0000'>organization: llor='#FF0000'>or='#FF0000'>512kb x 36; Vcc (V): 1.7 to 1.9 V
low Voltage Programmable Skew Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating Range: 0 to 70 C
Spread Spectrum Clock Generatlor='#FF0000'>or; Voltage(V): 3.3 V; Input Frequency Range: 25 MHz to 100 MHz; Output Frequency Range: 25 MHz to 100 MHz; Operating Range: 0 to 70 C; Package: SOIC
low Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating Range: 0 to 70 C
5V, 3.3V, ISR(TM) High-Perflor='#FF0000'>ormance CPlDs; # Macrocells: 6llor='#FF0000'>or='#FF0000'>4; Vcc (V): 3.3; fMax (MHz): 1llor='#FF0000'>or='#FF0000'>43; tPD (ns): 9 单芯位CMOS微机
5V, 3.3V, ISR(TM) High-Perflor='#FF0000'>ormance CPlDs; # Macrocells: 6llor='#FF0000'>or='#FF0000'>4; Vcc (V): 5; fMax (MHz): 15llor='#FF0000'>or='#FF0000'>4; tPD (ns): 6 单芯位CMOS微机
SINGlE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机
5V, 3.3V, ISR(TM) High-Perflor='#FF0000'>ormance CPlDs; # Macrocells: 6llor='#FF0000'>or='#FF0000'>4; Vcc (V): 3.3; fMax (MHz): 100; tPD (ns): 9 单芯位CMOS微机
5V, 3.3V, ISR(TM) High-Perflor='#FF0000'>ormance CPlDs; # Macrocells: 128; Vcc (V): 3.3; fMax (MHz): 83; tPD (ns): 10 单芯位CMOS微机
5V, 3.3V, ISR(TM) High-Perflor='#FF0000'>ormance CPlDs; # Macrocells: 6llor='#FF0000'>or='#FF0000'>4; Vcc (V): 5; fMax (MHz): 125; tPD (ns): 6 单芯位CMOS微机
Three-Pll General-Purpose EPROM Programmable Clock Generatlor='#FF0000'>or; Voltage (V): 3.3/5.0 V; Input Range: 1 MHz to 30 MHz; Output Range: .077 MHz to 100 MHz; Outputs: 6 单芯位CMOS微机
8-llor='#FF0000'>or='#FF0000'>mbit (512K x 16) MoBl(R) Static RAM; Density: 8 Mb; lor='#FF0000'>organization: llor='#FF0000'>or='#FF0000'>512kb x 16; Vcc (V): 2.20 to 3.60 V; 单芯位CMOS微机
High Speed low Voltage Programmable Skew Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 3.75 MHz to 110 MHz; Outputs: 8; Operating Range: 0 to 70 C 单芯位CMOS微机
3.3V SDRAM Buffer flor='#FF0000'>or Mobile PCs with llor='#FF0000'>or='#FF0000'>4 SO-DIMMs; Voltage (V): 3.3 V; Frequency Range: 0 MHz to 100 MHz; Outputs: 10; Operating Range: 0 to 70 C 单芯位CMOS微机
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 9; Operating Range: -llor='#FF0000'>or='#FF0000'>40 to 85 C 单芯位CMOS微机
Programmable Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating Range: -llor='#FF0000'>or='#FF0000'>40 to 85 C 单芯位CMOS微机
2-llor='#FF0000'>or='#FF0000'>mbit (128K x 16) Static RAM; Density: 2 Mb; lor='#FF0000'>organization: 128Kb x 16; Vcc (V): 3.0 to 3.6 V; 单芯位CMOS微机
MoBl(R) 1 llor='#FF0000'>or='#FF0000'>mbit (128K x 8) Static RAM; Density: 1 Mb; lor='#FF0000'>organization: 128Kb x 8; Vcc (V): 2.20 to 3.60 V; 单芯位CMOS微机
18-llor='#FF0000'>or='#FF0000'>mbit QDR(TM)-II SRAM 2-Wlor='#FF0000'>ord Burst Architecture; Architecture: QDR-II, 2 Wlor='#FF0000'>ord Burst; Density: 18 Mb; lor='#FF0000'>organization: 1Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
1-llor='#FF0000'>or='#FF0000'>mbit (128K x 8) Static RAM; Density: 1 Mb; lor='#FF0000'>organization: 128Kb x 8; Vcc (V): llor='#FF0000'>or='#FF0000'>4.50 to 5.50 V; 单芯位CMOS微机
llor='#FF0000'>or='#FF0000'>4-llor='#FF0000'>or='#FF0000'>mbit (256K x 18) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: llor='#FF0000'>or='#FF0000'>4 Mb; lor='#FF0000'>organization: lor='#FF0000'>256kb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
2-llor='#FF0000'>or='#FF0000'>mbit (6llor='#FF0000'>or='#FF0000'>4K x 32) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 2 Mb; lor='#FF0000'>organization: 6llor='#FF0000'>or='#FF0000'>4Kb x 32; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
200-MHz Field Programmable Zero Delay Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 10 MHz to 200 MHz; Outputs: 12; Operating Range: -llor='#FF0000'>or='#FF0000'>40 to 85 C 单芯位CMOS微机
2-llor='#FF0000'>or='#FF0000'>mbit (128K x 16) Static RAM; Density: 2 Mb; lor='#FF0000'>organization: 128Kb x 16; Vcc (V): 2.20 to 3.60 V; 单芯位CMOS微机
SINGlE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机
2-llor='#FF0000'>or='#FF0000'>mbit (256K x 8) Static RAM; Density: 2 Mb; lor='#FF0000'>organization: lor='#FF0000'>256kb x 8; Vcc (V): 2.20 to 3.60 V; 单芯8位CMOS微机
Very low Jitter Field and Factlor='#FF0000'>ory Programmable Clock Generatlor='#FF0000'>or; Voltage (V): 3.3 V; Input Range: 10 MHz to 133 MHz; Output Range: 20 MHz to 200 MHz; Outputs: 2 单芯位CMOS微机
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 5; Operating Range: 0 to 70 C 单芯位CMOS微机
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 5; Operating Range: -llor='#FF0000'>or='#FF0000'>40 to 85 C 单芯位CMOS微机
Three-Pll General Purpose FlASH Programmable Clock Generatlor='#FF0000'>or; Voltage (V): 3.3 V; Input Range: 1 MHz to 166 MHz; Output Range: 0 MHz to 200 MHz; Outputs: 3 单芯位CMOS微机
1:8 Clock Fanout Buffer; Voltage (V): 3.3 V; Frequency Range: 0 MHz to 350 MHz; Outputs: 8; Operating Range: -llor='#FF0000'>or='#FF0000'>40 to 85 C 单芯位CMOS微机
Quad Pll Clock Generatlor='#FF0000'>or with 2-Wire Serial Interface; Voltage (V): 2.5/3.3 V; Input Range: 27 MHz to 27 MHz; Output Range: llor='#FF0000'>or='#FF0000'>4.2 MHz to 166 MHz; Outputs: 5 单芯位CMOS微机
2.5V lor='#FF0000'>or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 MHz to 200 MHz; Outputs: 12; Operating Range: 0 to 70 C 单芯位CMOS微机
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 9; Operating Range: 0 to 70 C 单芯位CMOS微机
High Speed Multi-phase Pll Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 2llor='#FF0000'>or='#FF0000'>4 MHz to 200 MHz; Outputs: 11; Operating Range: 0 to 70 C 单芯位CMOS微机
2.5V lor='#FF0000'>or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 MHz to 200 MHz; Outputs: 18; Operating Range: -llor='#FF0000'>or='#FF0000'>40 to 85 C 单芯位CMOS微机
-bit AVR Microcontroller with 8K Bytes In- System Programmable Flash 位AVR微控制器具有8K字节的系统内可编程闪
2.5V lor='#FF0000'>or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 MHz to 200 MHz; Outputs: 12; Operating Range: 0 to 70 C
1:8 Clock Fanout Buffer; Voltage (V): 3.3 V; Frequency Range: 0 MHz to 350 MHz; Outputs: 8; Operating Range: 0 to 70 C
Spread Spectrum Clock Generatlor='#FF0000'>or; Voltage(V): 3.3 V; Input Frequency Range: llor='#FF0000'>or='#FF0000'>4 MHz to 32 MHz; Output Frequency Range: llor='#FF0000'>or='#FF0000'>4 MHz to 32 MHz; Operating Range: 0 to 70 C; Package: SOIC
High Speed low Voltage Programmable Skew Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 3.75 MHz to 110 MHz; Outputs: 8; Operating Range: 0 to 70 C
5V, 3.3V, ISR(TM) High-Perflor='#FF0000'>ormance CPlDs; # Macrocells: 6llor='#FF0000'>or='#FF0000'>4; Vcc (V): 3.3; fMax (MHz): 100; tPD (ns): 9
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| File Size |
1,602.57K /
119 Page |
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意法半导
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| Part No. |
M28Fllor='#FF0000'>or='#FF0000'>420
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| Description |
llor='#FF0000'>or='#FF0000'>4llor='#FF0000'>or='#FF0000'>mbit (llor='#FF0000'>or='#FF0000'>512kb llor='#FF0000'>or='#FF0000'>x8 lor='#FF0000'>or lor='#FF0000'>256kb lor='#FF0000'>x16, Boot Block) Flash Memlor='#FF0000'>ory(llor='#FF0000'>or='#FF0000'>4Mb闪速存储器)
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| File Size |
18.20K /
2 Page |
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Price and Availability
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