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clock-recovery Datasheet PDF File

For clock-recovery Found Datasheets File :: 10206 Search Time::1.453ms
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				Exar Corporation
Part No.	XRT75L00D XRT75L00DIV
OCR Text	...tter attenuator can be used for clock smoothing in SONET STS-1 to DS3 de-mapping. The XRT75L00D provides both Serial Microprocessor Interfac...Recovery circuit for high input jitter tolerance. * Meets E3/DS3/STS-1 Requirements. Jitte...
Description	E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
File Size	513.69K / 92 Page	View it Online	Download Datasheet

				Exar Corporation
Part No.	XRT75L06 XRT75L06IB
OCR Text	...2M MUX Peak Detector Slicer Clock & Data Recovery LOS Detector Clock Synthesizer Jitter Attenuator HDB3/ B3ZS Decoder RTIP_n RRing_n AGC/ Equalizer RxClk_n RxPOS_n RxNEG/LCV_n Local LoopBack Remote LoopBack RLOS_n TxCl...
Description	SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
File Size	341.00K / 63 Page	View it Online	Download Datasheet

				EXAR[Exar Corporation]
Part No.	XRT75R03DIV XRT75R03D
OCR Text	...able, Relayless * On chip Clock and Data Recovery circuit for high * Meets E3/DS3/STS-1 Jitter Tolerance Requirement * Detects and Clears LOS as per G.775 * Receiver Monitor mode handles up to 20 dB flat loss with 6 dB cable attenuat...
Description	THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER
File Size	749.20K / 134 Page	View it Online	Download Datasheet

				EXAR[Exar Corporation]
Part No.	XRT75R03IV XRT75R03
OCR Text	...ange APPLICATIONS * On chip Clock and Data Recovery circuit for high * Meets E3/DS3/STS-1 Jitter Tolerance Requirement * Detects and Clears LOS as per G.775 * Receiver Monitor mode handles up to 20 dB flat loss with 6 dB cable attenuat...
Description	THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
File Size	499.73K / 92 Page	View it Online	Download Datasheet

				EXAR[Exar Corporation]
Part No.	XRT75R06DIB XRT75R06D
OCR Text	...ter attenuators can be used for clock smoothing in SONET STS-1 to DS-3 de-mapping. The XRT75R06D provides a Parallel Microprocessor Interfac...Recovery LOS Detector Clock Synthesizer Jitter Attenuator HDB3/ B3ZS Decoder RTIP_n RRing_n ...
Description	SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
File Size	607.74K / 105 Page	View it Online	Download Datasheet

				Applied Micro Circuits Corp.
Part No.	S2065
OCR Text	...orating phase-locked loop (pll) clock synthesis from low speed reference ? quad receiver pll provides independent clock and data recovery for each channel ? internally series terminated ttl outputs ? on-chip 8b/10b line encoding and decodin...
Description	Quad Serial Backplane Device with Dual I/O(带双传送接收串行I/O的四收发
File Size	389.30K / 37 Page	View it Online	Download Datasheet

				Applied Micro Circuits Corp.
Part No.	S2064
OCR Text	...er with phase-locked loop (pll) clock synthesis from low speed reference ? quad receiver pll provides clock and data recovery ? internally series terminated ttl outputs ? on-chip 8b/10b line encoding and decoding for four separate parallel ...
Description	Quad Serial Backplane Device(用于以太网，光纤通道高速串行数据传送的四收发器)
File Size	347.69K / 33 Page	View it Online	Download Datasheet

				Applied Micro Circuits Corp.
Part No.	S2062
OCR Text	...er with phase-locked loop (pll) clock synthesis from low speed reference ? dual receiver pll provides clock and data recovery ? internally series terminated ttl outputs ? on-chip 8b/10b line encoding and decoding for two separate parallel 8...
Description	Dual Serial Backplane Transceiver(用于以太网，光纤通道高速串行数据传送的双收发器)
File Size	295.75K / 27 Page	View it Online	Download Datasheet

				Applied Micro Circuits Corp.
Part No.	S2061
OCR Text	clock generator ? device specification serial backplane transceiver s2061 features ? transmitter incorporates phase-locked loop (pll) provid...recovery ? 1.0 C 1.25 gbps operation ? 8-bit parallel ttl compatible interface ? 1.6w typical power ...
Description	Serial Backplane Transceiver(用于高速串行数据传送的收发
File Size	144.16K / 16 Page	View it Online	Download Datasheet

				Applied Micro Circuits Corp.
Part No.	S2004
OCR Text	...er with phase-locked loop (pll) clock synthesis from low speed reference ? quad receiver pll provides clock and data recovery ? internally series terminated ttl outputs ? on-chip 8b/10b line encoding and decoding for four separate parallel ...
Description	Quad Serial Backplane Device(用于高速串行数据传送的四串行收发器)
File Size	386.12K / 38 Page	View it Online	Download Datasheet

For clock-recovery Found Datasheets File :: 10206 Search Time::1.453ms
Page :: | 1 | 2 | <3> | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 |