|
|
|
|
Part No. |
MB95108AMPFM
|
OCR Text |
... falling, or both edges can be selected) can be used to recover from lo w-power consumption (standby) modes. ? 8/10-bit a/d converter 8-bit or 10-bit resolution can be selected ? low-power consumption (standby) mode stop mode sl... |
Description |
8-BIT, MROM, 16.25 MHz, MICROCONTROLLER, PQFP64
|
File Size |
1,851.96K /
72 Page |
View
it Online |
Download Datasheet |
|
|
|
RALTRON[Raltron Electronics Corporation]
|
Part No. |
SY10
|
OCR Text |
...The output frequency tracks the selected input reference. The "Locked to Reference Modes" is typically used when a slave clock source is synchronized to the network. In these modes, the SY10 provides timing signals, which are synchronized, ... |
Description |
SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT
|
File Size |
253.46K /
21 Page |
View
it Online |
Download Datasheet |
|
|
|
HYNIX SEMICONDUCTOR INC
|
Part No. |
HMT325S6BFR6C-H9
|
OCR Text |
... operations continue. rank 0 is selected by s0 ; rank 1 is selected by s1 . odt[1:0] in active high asserts on-die termination for dq, dm, dqs, and dqs signals if enabled via the ddr3 sdram mode register. r as , cas , we in active low w... |
Description |
256M X 64 DDR DRAM MODULE, DMA204
|
File Size |
474.71K /
54 Page |
View
it Online |
Download Datasheet |
|
|
|
MICREL[Micrel Semiconductor]
|
Part No. |
SY58029U_07 SY58029U SY58029UMG SY58029UMGTR SY58029UMI SY58029UMITR
|
OCR Text |
...ts s Provides two copies of the selected input s Guaranteed AC performance over temperature and voltage: * DC-to-> 5Gbps data rate throughput * < 390ps IN-to-Out tpd * < 110ps tr / tf times s Ultra low-jitter design: * < 10psPP total jitter... |
Description |
ULTRA PRECISION DIFFERENTIAL LVPECL 4:1 MUX with 1:2 FANOUT and INTERNAL TERMINATION
|
File Size |
198.54K /
11 Page |
View
it Online |
Download Datasheet |
|
|
|
MICREL[Micrel Semiconductor]
|
Part No. |
SY87721LHITR SY87721L SY87721LHG SY87721LHGTR SY87721LHI
|
OCR Text |
...ference clock frequency and the selected divide ratio. On-chip clock generation is performed through the use of a frequency multiplier PLL with a byte rate or code group rate source as reference.
SIMPLIFIED BLOCK DIAGRAM
SY87721L AnyRat... |
Description |
3.3V 28Mbps-2.7Gbps ANYRATE CLOCK AND DATA RECOVERY WITH INTEGRATED CLOCK MULTIPLIER UNIT
|
File Size |
159.11K /
15 Page |
View
it Online |
Download Datasheet |
|
Price and Availability
|