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For rams Found Datasheets File :: 2552    Search Time::1.688ms    
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    INNOVASIC[InnovASIC, Inc]
INNOVASIC[InnovASIC Inc]
Part No. L64250JC20 IA64250 IA64250-PLC68M L64250JC15
OCR Text ... input data for the LUT and ACC rams, the select lines for both the output mux and the shifter, and the reset for the FP counter. This block also controls the clearing of the ACC RAM. The ACC RAM stores the video data that is to be output d...
Description Histogram/Hough Transform Processor

File Size 99.66K  /  21 Page

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    MOTOROLA INC
NEC, Corp.
Motorola Mobility Holdings, Inc.
Motorola, Inc.
Part No. MCM63P818 MCM63P736 MCM63P736TQ100 MCM63P736ZP133R MCM63P818TQ100R MCM63P818ZP100R MCM63P818ZP66 MCM63P818ZP66R
OCR Text ... 4M bit synchronous fast static rams designed to provide a burstable, high performance, secondary cache for the PowerPCTM and other high performance microprocessors. The MCM63P736 is organized as 128K words of 36 bits each and the MCM63P818...
Description Circular Connector; Body Material:Aluminum; Series:PT07; No. of Contacts:2; Connector Shell Size:8; Connecting Termination:Solder; Circular Shell Style:Jam Nut Receptacle; Circular Contact Gender:Pin; Insert Arrangement:8-2
128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM 256K X 18 CACHE SRAM, 5 ns, PQFP100
128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM 128K X 36 CACHE SRAM, 4 ns, PBGA119
128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM 128K X 36 CACHE SRAM, 5 ns, PQFP100
Replaced by PTH12000W :

File Size 320.35K  /  20 Page

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    MPC2105CDG66 MPC2106CDG66 MPC2105C

Motorola, Inc
Part No. MPC2105CDG66 MPC2106CDG66 MPC2105C
OCR Text ...ress bit when asynchronous Data rams are used. Next to least significant address bit when asynchronous Data rams are used. Data RAM Address Strobe - For MPC2105C use ADS0 only. For MPC2106C use ADS0, ADS1.. Data RAM Address Latch Enable - U...
Description 512KB and 1MB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms

File Size 228.90K  /  18 Page

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    MPC2104P MPC2104PDG66 MPC2105PDG66

Motorola, Inc
Part No. MPC2104P MPC2104PDG66 MPC2105PDG66
OCR Text ... two of the 3.3 V 32K x 32 data rams. The MPC2105P is configured as 64K x 64 bits and uses two of the 3.3 V 64K x 32 data rams. Both modules are in a 178 (89 x 2) pin DIMM format. For tag bits on the 2104P, a 5 V cache tag RAM configured as...
Description 256KB/512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms

File Size 158.27K  /  16 Page

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    GS8170DW72AC-300I GS8170DW36AC-300I GS8170DW36AC-250I GS8170DW36AC-333 GS8170DW36AC-350 GS8170DW36AC-350I GS8170DW36AC-3

GSI Technology
Part No. GS8170DW72AC-300I GS8170DW36AC-300I GS8170DW36AC-250I GS8170DW36AC-333 GS8170DW36AC-350 GS8170DW36AC-350I GS8170DW36AC-333I GS8170DW36AGC-350 GS8170DW72AGC-350 GS8170DW36AGC-350I GS8170DW72AGC-350I GS8170DW72AC-333 GS8170DW72AC-333I GS8170DW72AC-250 GS8170DW72AC-250I GS8170DW72AC-350 GS8170DW72AC-350I GS8170DW36AGC-250 GS8170DW72AGC-250 GS8170DW36AGC-250I GS8170DW72AGC-250I GS8170DW36AGC-300 GS8170DW72AGC-300 GS8170DW72AGC-300I GS8170DW72AGC-333 GS8170DW72AGC-333I GS8170DW36AGC-333 GS8170DW36AGC-333I GS8170DW36AGC-300I GS8170DW36AC-350IT
OCR Text ...simplifies input signal timing. rams support pipelined reads utilizing a rising-edgetriggered output register. They also utilize a Dual Cycle Deselect (DCD) output deselect protocol. rams are offered in a number of configurations includi...
Description 512K X 36 STANDARD SRAM, 1.6 ns, PBGA209
18Mb Σ1x1Dp CMOS I/O Double Late Write SigmaRAM

File Size 757.26K  /  32 Page

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    DS1221

Dallas Semiconductor
Dallas Semiconducotr
Part No. DS1221
OCR Text ...EAD. FEATURES Converts CMOS rams into nonvolatile memories Data is automatically protected during power loss 2-to-4 decoder provides for up to 4 CMOS rams Provides for redundant batteries Test battery condition on power-up Full 10% oper...
Description Nonvolatile Controller x 4 Chip

File Size 132.87K  /  8 Page

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    MPC2107SG15 MPC2104 MPC2104SG66 MPC2105SG66 MPC2106SG66

Motorola, Inc
MOTOROLA[Motorola Inc]
Part No. MPC2107SG15 MPC2104 MPC2104SG66 MPC2105SG66 MPC2106SG66
OCR Text ...ynchronous or asynchronous data rams. The MPC2104, MPC2105, and MPC2106 utilize synchronous Burstrams. The modules are configured as 32K x 72, 64K x 72, and 128K x 72 bits in a 182 (91 x 2) pin DIMM format. The MPC2104 uses four of Motorola...
Description 256KB and 512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms

File Size 227.97K  /  24 Page

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    IDT7198L IDT7198L20DB IDT7198L20EB IDT7198L20LB IDT7198L25DB IDT7198L25EB IDT7198L25LB IDT7198L35DB IDT7198L35EB IDT7198

IDT[Integrated Device Technology]
Part No. IDT7198L IDT7198L20DB IDT7198L20EB IDT7198L20LB IDT7198L25DB IDT7198L25EB IDT7198L25LB IDT7198L35DB IDT7198L35EB IDT7198L35LB IDT7198L45DB IDT7198L45EB IDT7198L45LB IDT7198L55DB IDT7198L55EB IDT7198L55LB IDT7198L70DB IDT7198L70EB IDT7198L70LB IDT7198L85DB IDT7198L85EB IDT7198L85LB IDT7198S IDT7198S20DB IDT7198S20EB IDT7198S20LB IDT7198S25DB IDT7198S25EB IDT7198S25LB IDT7198S35DB IDT7198S35EB IDT7198S35LB IDT7198S45DB IDT7198S45EB IDT7198S45LB IDT7198S55DB IDT7198S55EB IDT7198S55LB IDT7198S70DB IDT7198S70EB IDT7198S70LB IDT7198S85DB IDT7198S85EB IDT7198S85LB IDT7198LS70DB
OCR Text rams 64K (16K x 4-BIT) Added Chip Select and Output Controls IDT7198S IDT7198L Integrated Device Technology, Inc. FEATURES: * Fast Output Enable (OE) pin available for added system flexibility * Multiple Chip Selects (CS1, CS2) s...
Description CMOS static RAM 64K (16K x 4-bit)
CMOS STATIC rams 64K (16K x 4-BIT) Added Chip Select and Output Controls

File Size 80.86K  /  8 Page

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    GS8171DW72AC-300 GS8171DW36AC-300 GS8171DW36AC-300I GS8171DW36AC-250 GS8171DW36AC-333 GS8171DW36AC-333I GS8171DW36AC-350

GSI Technology
Part No. GS8171DW72AC-300 GS8171DW36AC-300 GS8171DW36AC-300I GS8171DW36AC-250 GS8171DW36AC-333 GS8171DW36AC-333I GS8171DW36AC-350I GS8171DW72AC-250I GS8171DW72AC-333I GS8171DW72AC-300I GS8171DW72AC-350 GS8171DW72AC-350I
OCR Text ...simplifies input signal timing. rams support pipelined reads utilizing a rising-edgetriggered output register. They also utilize a Dual Cycle Deselect (DCD) output deselect protocol. rams are offered in a number of configurations includi...
Description 18Mb ??x1Dp HSTL I/O Double Late Write SigmaRAM
18Mb B>1x1Dp HSTL I/O Double Late Write SigmaRAM
18Mb Σ1x1Dp HSTL I/O Double Late Write SigmaRAM

File Size 763.93K  /  33 Page

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