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INTEGRATED DEVICE TECHNOLOGY INC
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Part No. |
ICS932S200BG-T ICS932S200BFLFT ICS932S200BGT
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OCR Text |
...ow state. 36 cpu_stop# in this asychronous input halts the cpuclk and the 3v66 clocks at logic "0" when driven active ( low ) . 37 pci_stop# in this asynchronous input halts the pciclk at logic"0" when driven active(low). pciclk_f is no... |
Description |
133 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
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File Size |
130.21K /
14 Page |
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it Online |
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Micron
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Part No. |
MT16JTF1G64AZ MT16JTF25664AZ MT16JTF51264AZ
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OCR Text |
...reset: reset# is an active low asychronous input that is connected to each dram and the registering clock driver. after reset# goes high, the dram must be reinitial- ized as though a normal power-up was executed. sx# input chip select: en... |
Description |
DDR3 SDRAM UDIMM
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File Size |
432.62K /
18 Page |
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it Online |
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Advanced Micro Devices, Inc.
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Part No. |
PALCE29MA16
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OCR Text |
...lled clocks can also be used in asychronous application. v 1
0 preset reset s2 s3 1 1
1 0
0 1
0 0 s4 s5 common i/ oe (pin) individual oe individual asynchronous preset p0 p7 or p11 common clk/ le (pin) individual clk/ le indiv... |
Description |
24-Pin EE CMOS Programmable Array Logic
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File Size |
295.17K /
25 Page |
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it Online |
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