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  pecl lvds Datasheet PDF File

For pecl lvds Found Datasheets File :: 1258    Search Time::1.484ms    
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    Linear
Part No. LTC1747 1747F
OCR Text ...y be driven differentially from pecl, GTL and other low swing logic families or from single-ended TTL or CMOS. The low noise, high gain ENC ...lvds. When using a single-ended encode signal asymmetric rise and fall times can result in duty cycl...
Description 12-Bit, 80Msps Low Noise ADC
From old datasheet system

File Size 502.72K  /  20 Page

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    LTC2221 22201F LTC2220

Linear Technology
Part No. LTC2221 22201F LTC2220
OCR Text ... single ended with a sine wave, pecl, lvds, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. APPLICATIO S Wireless and Wired Broadband Commu...
Description From old datasheet system
12-Bit,170Msps/135Msps ADCs

File Size 700.51K  /  28 Page

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    MAXIM[Maxim Integrated Products]
Part No. MAX3905 MAX3905_D
OCR Text ... single-ended TTL, differential pecl or lvds input data, and provides bias and modulation currents for driving a VCSEL. The output is DC-coupled to the VCSEL to minimize component count. The driver provides temperature compensation to VCSEL...
Description From old datasheet system
150Mbps Automotive VCSEL Driver

File Size 1,141.93K  /  13 Page

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    NB4L52

ON Semiconductor
Part No. NB4L52
OCR Text ...ion Techniques - Designing with pecl (ECL at +5.0 V) - ECLinPS I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between lvds and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes...
Description 2.5 to 5.5V ECL D-Flip-flop w/Diff Reset & Input Terms
From old datasheet system

File Size 66.58K  /  8 Page

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    ONSEMI[ON Semiconductor]
Part No. NB6L11 NB6L11DTR2 NB6L11D NB6L11DR2 NB6L11DT
OCR Text ...75 ps Typical Rise/Fall Times * pecl Mode Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V * NECL Mode Operating Range: VCC = 0 V wi...lvds, LVpecl, LVNECL, LCMOS, LVTTL and CML Input Compatible *For additional marking information,...
Description 2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVpecl/LVNECL 1:2 CLOCK OR DATA FANOUT BUFFER / TRANSLATOR 6L SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
6GHz 2.5V/3.3V Multilevel Input to Differential LVNECL/LVpecl 1:2 Clock or Data Fanout Buffer/Transl
From old datasheet system

File Size 112.11K  /  12 Page

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    on
Part No. NB6L16
OCR Text ...ngle-Ended Input - VBB Output * pecl Mode Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V * NECL Mode Operating Range: VCC = 0 V with VEE = -2.375 V to -3.465 V * Open Input Default State * lvds, LVpecl, LVNECL, LVCMOS, LVTTL and C...
Description 6GHz/6Gbps 2.5V/3.3V Multi-level Input to Differential LVECL Clock or Data Translator/Receiver/Drive
From old datasheet system

File Size 112.87K  /  12 Page

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    SY89112U SY89113UMGTR SY89113U SY89113UMG

MICREL[Micrel Semiconductor]
Part No. SY89112U SY89113UMGTR SY89113U SY89113UMG
OCR Text ...when configured in single-ended pecl input mode. VBB1 can be used for AC-coupling of CLK1, see Figure 4d for details. Maximum sink/source cu...lvds Outputs: These lvds output pairs are the precision, low skew copies of the selected input. Plea...
Description 2.5V Low Jitter, Low Skew 1:12 lvds Fanout Buffer with 2:1 Input MUX and Intermal Termination
From old datasheet system

File Size 620.73K  /  14 Page

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    CB55000 8590

ST Microelectronics
STMicroelectronics
Part No. CB55000 8590
OCR Text ...oltage CMOS. - Low Voltage TTL, pecl, HSTL, SSTL, lvds, PCI. s AGP 2X and 4X, USB to support 2.5 V and 3.3 V I/O interface according to EIA/JESD 8A specification. s Drive capability up to 8 mA per buffer with slew rate control, current spik...
Description HCMOS7 STANDARD CELLS
From old datasheet system
HCMOS7 STANDARD CELLS

File Size 2,532.22K  /  15 Page

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For pecl lvds Found Datasheets File :: 1258    Search Time::1.484ms    
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