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Integrated Device Techn...
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Part No. |
82P33814ANLG8 82P33814ANLG/W
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OCR Text |
... and out10 output clocks n*8khz multi- ples up to 100 mhz ? dpll1 and dpll2 support independent programmable delays for each of in1 to in6; ...mode the dplls synthesize clocks based on the system clock alone. in locked mode the dplls filter ... |
Description |
Synchronization Management Unit for IEEE 1588 and Synchronous Ethernet
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File Size |
344.74K /
13 Page |
View
it Online |
Download Datasheet
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Integrated Device Techn...
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Part No. |
82P33810ABAG8
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OCR Text |
... and out11 output clocks n*8khz multi- ples up to 100 mhz ? dpll1 and dpll2 support independent programmable delays for each of in3 to in14;...mode the dplls synthesize clocks based on the system clock alone. in locked mode the dplls filter ... |
Description |
Synchronization Management Unit for IEEE 1588 and Synchronous Ethernet
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File Size |
279.59K /
13 Page |
View
it Online |
Download Datasheet
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![](images/bg04.gif) |
Integrated Device Techn...
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Part No. |
82P33724
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OCR Text |
...and out10 output clocks n*8 khz multi- ples up to 100 mhz ? dpll1 and dpll2 support independent programmable delays for each of in1 to in16;...mode the dplls synthesize clocks ba sed on the system clock alone. in locked mode the dplls filter ... |
Description |
Port Synchronizer for IEEE 1588 and Synchronous Ethernet
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File Size |
232.45K /
13 Page |
View
it Online |
Download Datasheet
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Price and Availability
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